ADC Theory of Operation
1. Signal Capture
The ADC samples the differential voltage between its positive and negative input pins (e.g., INA+ and INA−) on the rising edge of CLK±. It is the difference between the two pins that matters, not their absolute voltages. This differential architecture rejects common-mode noise and interference.
2. Analog-to-Digital Conversion
After capturing the input, the ADC compares the sampled voltage against an internal reference to produce a 12-bit signed (2's complement) digital output code, ranging from −2048 to +2047.
The polarity rule is:
| Condition | Output |
|---|---|
| INA+ > INA− | Positive 2's complement code (0 to +2047) |
| INA− > INA+ | Negative 2's complement code (−2048 to 0) |
| INA+ = INA− | Code = 0 |
3. The Transfer Equation
The relationship between the digital output code and the actual input voltage is:
Where:
- V_IN — the reconstructed differential input voltage (V)
- V_FS — the full-scale input voltage (default 0.8 V_PP-DIFF, adjustable via
FS_RANGE) - Code — the signed decimal output (−2048 to +2047 for 12-bit)
- N — ADC resolution = 12 bits, so 2^N = 4096
4. Worked Examples
Assume default full-scale: V_FS = 0.8 V_PP-DIFF, N = 12.
Example A — Positive full-scale input:
- INA+ is 0.4 V above INA−
- Code = +2047 (just below positive clip)
- V_IN = 0.8 × (2047 / 4096) ≈ +0.3998 V ✓
Example B — Negative full-scale input:
- INA− is 0.4 V above INA+
- Code = −2048 (negative clip)
- V_IN = 0.8 × (−2048 / 4096) = −0.4 V ✓
Example C — Zero differential:
- INA+ = INA−
- Code = 0
- V_IN = 0.8 × (0 / 4096) = 0 V ✓
Example D — Mid-scale positive:
- Code = +1024
- V_IN = 0.8 × (1024 / 4096) = +0.2 V
5. LSB Size
The voltage represented by one LSB (least significant bit) is:
This is the smallest voltage change the ADC can resolve.
6. Full-Scale Adjustment (FS_RANGE)
The FS_RANGE register allows V_FS to be programmed between approximately 0.5 V_PP and 1.04 V_PP (per the DC Specifications). Increasing V_FS reduces sensitivity (larger LSB) but accommodates larger input swings without clipping. Decreasing V_FS improves sensitivity (smaller LSB) for small signals. The same equation applies — only V_FS changes.
7. Saturation / Overrange
If the differential input exceeds ±V_FS/2, the output saturates:
- V_IN > +V_FS/2 → Code locks at +2047
- V_IN < −V_FS/2 → Code locks at −2048
The device's fast overrange detection outputs (ORA–ORD pins) assert high when this threshold is exceeded, providing a hardware warning flag independent of the JESD204C data path.