Channel vs. Converter
Each channel has its own dedicated ADC core. The ADC12QJ1600-EP is explicitly described as a non-interleaved architecture.
The ADC12QJ1600-EP uses a non-interleaved architecture, meaning each of the four channels has its own fully independent, dedicated ADC core running simultaneously.
What "Non-Interleaved" Means
Non-Interleaved (this device) vs. Interleaved
It helps to contrast the two architectures:
Interleaved architecture — one fast ADC is faked by time-sharing multiple slower ADC cores. For example, to reach 1.6 GSPS, you might use 4 cores each running at 400 MSPS, taking turns on the same input. Each core samples at a different phase offset.
Input ──┬──► Core 1 (samples at t=0, 4, 8 ns...)
├──► Core 2 (samples at t=1, 5, 9 ns...)
├──► Core 3 (samples at t=2, 6, 10 ns...)
└──► Core 4 (samples at t=3, 7, 11 ns...)
└──► Combined = 1.6 GSPS stream
Problems: any mismatch between cores (gain, offset, timing) creates spurious tones in the output spectrum — a well-known artifact called interleaving spurs.
Non-interleaved architecture (ADC12QJ1600-EP) — each channel has its own fully independent ADC core running at the full 1.6 GSPS natively. The channels do not share cores or take turns.
INA± ──► ADC Core A ──► 12-bit output @ 1.6 GSPS
INB± ──► ADC Core B ──► 12-bit output @ 1.6 GSPS
INC± ──► ADC Core C ──► 12-bit output @ 1.6 GSPS
IND± ──► ADC Core D ──► 12-bit output @ 1.6 GSPS
└──► All four fed into JESD204C framer
What Each Channel Gets
Each of the four channels has its own dedicated:
| Resource | Per-Channel? | Notes |
|---|---|---|
| Differential input pair (e.g. INA+/INA−) | Yes | Separate pins |
| ADC core (sample-and-hold + comparator) | Yes | Full 1.6 GSPS native |
| Calibration engine | Yes | Independent offset/gain cal |
| Full-scale range register | Yes | FS_RANGE_A/B/C/D per channel |
| Offset register | Yes | OFSx per channel |
| Overrange detector | Yes | ORA, ORB, ORC, ORD pins |
| Timestamp insertion logic | Yes | Each channel can embed a timestamp |
All four cores share a single CLK± input and a single JESD204C serializer/framer, but the analog conversion path is entirely separate per channel.
Why This Matters
The non-interleaved design has two major practical benefits:
No interleaving spurs. Since no core time-shares an input, there are no periodic mismatch errors between sub-ADCs. The device's SFDR (64 dBc at 100 MHz) is clean of that artifact class.
True simultaneous sampling. All four channels capture their inputs on the same CLK± rising edge. There is no phase offset between channels — which is essential for phased-array radar, multi-channel oscilloscopes, and beamforming receivers where phase coherence between channels is critical.
The JESD204C parameter M = 4 in all quad-channel JMODEs directly reflects this: four independent converters each producing their own 12-bit sample stream every clock cycle, all multiplexed together onto the shared SerDes lanes.