Transport Layer Layout

TI ADC12QJ1600-EP

JMODE 15 configuration parameters:

• Operating Mode: 12-Bit, 64B/66B, 8 Lanes
• Encoding: 64B/66B
• N: 12 bits per sample
• N’: 12 bits per sample
• CS: 0 control bits per sample
• CF: 0 control words per frame
• L: 8 lanes
• M: 8 lanes
• F: 3 octets (bytes) per frame per lane
• S: 2 samples per converter per frame
• HD: High-density format, sample split between lanes
• E: 3 multiblocks per extended multiblock

Transport Layer Data Formate for JMODE 15

Table 6-29. JMODE 15 (12-bit, Dual/Single channel only, 8/4 lanes, 64B/66B)

OCTET	0		1		2
NIBBLE	0	1	2	3	4	5
D0	A0			A4
D1	A1			A5
D2	A2			A6
D3	A3			A7
D4	B0			B4
D5	B1			B5
D6	B2			B6
D7	B3			B7

Celine note for JMODE 15

Data mapping with 128 bit Rx IP

• Channel A: 4 lanes
• block: 64B/66B (significant digit: 64(8 octets))
• multiblock: 32 blocks (significant digit: 32*8(octets))
• extended multiblock: 3 multiblocks (significant digit: 3328(octets))
• ADC resolution: 12 bits (significant digit: 12 bits(1.5 octets))
• sample: 3328(octets)/(1.5 octets/sample) = 512 samples
• Rx data length: 128 bits (16 octets) = 10 + 2/3 samples
• Rx Length in 512 samples: 512 samples / (10 + 2/3) samples = 48

Celine note for Channel A

JMODE 15 (12-bit, Single channel only, 4 lanes, 64B/66B) Rx IP Data Mapping [127:64]

OCTET	0		1		2		3		4		5		6		7
NIBBLE	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
D0	A0			A4			A8			A12			A16			A20[11:8]
D1	A1			A5			A9			A13			A17			A21[11:8]
D2	A2			A6			A10			A14			A18			A22[11:8]
D3	A3			A7			A11			A15			A19			A23[11:8]

JMODE 15 (12-bit, Single channel only, 4 lanes, 64B/66B) Rx IP Data Mapping [63:0]

OCTET	8		9		10		11		12		13		14		15
NIBBLE	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
D0	A20[7:0]		A24			A28			A32			A36			A40[11:4]
D1	A21[7:0]		A25			A29			A33			A37			A41[11:4]
D2	A22[7:0]		A26			A30			A34			A38			A42[11:4]
D3	A23[7:0]		A27			A31			A35			A39			A43[11:4]

JMODE 6 configuration parameters:

• operating mode: 12-bit, 64B/66B, 6 lanes
• Encoding: 64B/66B
• N: 12 bits per sample
• N’: 12 bits per sample
• CS: 0 control bits per sample
• CF: 0 control words per frame
• L: 6 lanes
• M: 4 converters
• F: 2 octets (bytes) per frame per lane
• S: 2 samples per converter per frame
• HD: high density mode, samples split between lanes
• E: 1 multiblock per extended multiblock

Transport Layer Data Format for JMODE 6

Table 6-24. JMODE 6 (12-bit, 6/3/2 lanes, 64B/66B)

OCTET	0		1
NIBBLE	0	1	2	3
D0	A0[11:0]			A1[11:8]
D1	A1[7:0]		B0[11:4]
D2	B0[3:0]	B1[11:0]
D3	C0[11:0]			C1[11:8]
D4	C1[7:0]		D0[11:8]
D5	D0[3:0]	D1[11:0]

Celine note for JMODE 6

Data mapping with 128 bit Rx IP

• Channel A: 6 lanes
• block: 64B/66B (significant digit: 64(8 octets))
• multiblock: 32 blocks (significant digit: 32*8(octets))
• extended multiblock: 1 multiblock (significant digit: 32*8(octets))
• ADC resolution: 12 bits (significant digit: 12 bits(1.5 octets))

Celine note for 4 channels output layout (JMODE 6)

JMODE 6 (12-bit, 6 lanes, [123:64], 4 channels)

OCTET	0		1		2		3		4		5		6		7
NIBBLE	0	1	2	3	4	5	6	7	8	9	10	11	12	13	14	15
D0	A0[11:0]			A1[11:8]	A2[11:0]			A3[11:8]	A4[11:0]			A5[11:8]	A6[11:0]			A7[11:8]
D1	A1[7:0]		B0[11:4]		A3[7:0]		B1[11:4]		A5[7:0]		B2[11:4]		A7[7:0]		B3[11:4]
D2	B0[3:0]	B1[11:0]			B2[3:0]	B3[11:0]			B4[3:0]	B5[11:0]			B6[3:0]	B7[11:0]
D3	C0[11:0]			C1[11:8]	C2[11:0]			C3[11:8]	C4[11:0]			C5[11:8]	C6[11:0]			C7[11:8]
D4	C1[7:0]		D0[11:8]		C3[7:0]		D1[11:8]		C5[7:0]		D2[11:8]		C7[7:0]		D3[11:8]
D5	D0[3:0]	D1[11:0]			D2[3:0]	D3[11:0]			D4[3:0]	D5[11:0]			D6[3:0]	D7[11:0]

tip

  parameter BRAM_DATA_WIDTH = 12;

  logic[BRAM_DATA_WIDTH-1:0] A[0:15];

  assign A[0] = rx_lane_data_0[123-:12];
  assign A[1] = {rx_lane_data_0[111-:4], 8'h00} | {4'h0, rx_lane_data_1[123-:8]};
  assign A[2] = rx_lane_data_0[107-:12];
  assign A[3] = {rx_lane_data_0[95-:4], 8'h00} | {4'h0, rx_lane_data_1[107-:8]};
  assign A[4] = rx_lane_data_0[91-:12];
  assign A[5] = {rx_lane_data_0[79-:4], 8'h00} | {4'h0, rx_lane_data_1[91-:8]};
  assign A[6] = rx_lane_data_0[75-:12];
  assign A[7] = {rx_lane_data_0[63-:4], 8'h00} | {4'h0, rx_lane_data_1[75-:8]};
  assign A[8] = rx_lane_data_0[59-:12];
  assign A[9] = {rx_lane_data_0[47-:4], 8'h00} | {4'h0, rx_lane_data_1[59-:8]};
  assign A[10] = rx_lane_data_0[43-:12];
  assign A[11] = {rx_lane_data_0[31-:4], 8'h00} | {4'h0, rx_lane_data_1[43-:8]};
  assign A[12] = rx_lane_data_0[27-:12];
  assign A[13] = {rx_lane_data_0[15-:4], 8'h00} | {4'h0, rx_lane_data_1[27-:8]};
  assign A[14] = rx_lane_data_0[11-:12];
  assign A[15] = {rx_lane_data_0[3-:4], 8'h00} | {4'h0, rx_lane_data_1[11-:8]};

JMODE 6 (12-bit, 6 lanes, [63:0], 4 channels)

OCTET	8		9		10		11		12		13		14		15
NIBBLE	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31
D0	A8[11:0]			A9[11:8]	A10[11:0]			A11[11:8]	A12[11:0]			A13[11:8]	A14[11:0]			A15[11:8]
D1	A9[7:0]		B8[11:4]		A11[7:0]		B9[11:4]		A13[7:0]		B10[11:4]		A15[7:0]		B11[11:4]
D2	B8[3:0]	B9[11:0]			B10[3:0]	B11[11:0]			B12[3:0]	B13[11:0]			B14[3:0]	B15[11:0]
D3	C8[11:0]			C9[11:8]	C10[11:0]			C11[11:8]	C12[11:0]			C13[11:8]	C14[11:0]			C15[11:8]
D4	C9[7:0]		D8[11:8]		C11[7:0]		D9[11:8]		C13[7:0]		D10[11:8]		C15[7:0]		D11[11:8]
D5	D8[3:0]	D9[11:0]			D10[3:0]	D11[11:0]			D12[3:0]	D13[11:0]			D14[3:0]	D15[11:0]

ADC theory of operation

The differential voltages at the analog inputs are captured by the rising edge of CLK±. After capturing the input signal the ADC converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the voltage on the negative input (that is, INA–) is higher than the voltage on the positive input (that is, INA+) then the digital output is a negative 2's complement value. If the voltage on the positive input is higher than the voltage on the negative input then the digital output is a positive 2's complement value. Equation 1 can calculate the differential voltage at the input pins from the digital output.

V_IN = Code / 2^N * V_FS Equation 1.

Where:

• Code is the signed decimal output code (for example, -2048(12'h800) to +2047(12'h7FF))
• N is the ADC resolution
• V<sub>FS</sub> is the full-scale input voltage of the ADC as specified in the DC Specifications table, including any adjustment performed by programming FS_RANGE

Celine note for ADC resolution

For V_FS = 1 V, the ADC resolution is 12 bits, the the LSB (least significant bit) is :

V_LSB = V_FS / 2¹² = 1/4096 = 244.140625 μV

Condition	Output
INA+ > INA−	Positive 2's complement code (0 to +2047)
INA− > INA+	Negative 2's complement code (−2048 to 0)
INA+ = INA−	Code = 0

1. Positive 2's complement code (0 to +2047)

• positive full-scale +2047 (0x7FF)
  • Code = +2047 (12'h7FF)
  • V_IN = (2047/4096) * 1V = 0.499755859375 V ≈ 0.5 V

2. Negative 2's complement code (−2048 to 0)

• negative full-scale -2048 (0x800)

  • Code = -2048 (12'h800)
    • 12'h800 = 12'b1000 0000 0000 0000 = (-1) * 2¹¹ = -2048
  • V_IN = (−2048/4096) * 1V = −0.5 V

• any other negative code

  • Code = -2033(12'h80F)

    • 12'h80F = 12'b1000 0000 1111 = (-1) * 2¹¹ + 2³ + 2² + 2¹ + 2⁰ = -2033

  • V_IN = (−2033/4096) * 1V = -0.496337890625 V

  • Code = -1 (12'hFFF)

    • 12'hFFF = 12'b1111 1111 1111 1111 = (-1) * 2¹¹ + 2¹⁰ + 2⁹ + 2⁸ + 2⁷ + 2⁶ + 2⁵ + 2⁴ + 2³ + 2² + 2¹ + 2⁰ = -1

  • V_IN = (−1/4096) * 1V = -0.000244140625 V

tip

Reframed code as (sign digit(MSB) + absolute value) to make sure the code don't use the 2's complement code.
Then the normalization for negtive code can be done in the same way as positive code except the sign digit is inverted.

logic [11:0] code;
// code_reframed[11] = code[11]: signed digit; 
// code_reframed[10:0] = abs(code[10:0]);
logic [11:0] code_reframed; 

alaways_comb begin
  if(code = 0) begin
    code_reframed = '0;
  end else if (code[11]) begin
    code_reframed = (~(code - 1)) | 12'h800;
  end else begin
    code_reframed = code;
  end
end