Transmit Latency

The latency variation is critical for JESD204C systems. The transmit latency through the IP core is fixed but the transceiver introduces some variation as the internal transmit elastic buffer of the transceiver is included in the data path. The 8B10B and 64B66B transmit data path latencies are shown in the following tables, respectively. They do not include the latency through the JESD204_PHY IP core if using UltraScale/UltraScale+, or the GT Quad/GT Wizard subsystem if using Versal Adaptive SoCs (GTdelay).

If using UltraScale or UltraScale+ the transmit latency through the JESD204_PHY IP core is equal to the latency through the GT (GTdelay). There is no additional latency added by the JESD204_PHY IP core. Refer to the relevant GT for the PHY latency values.

Table: 8B10B Transmit Data Path Latency Through JESD204C

	GTME5 Transceiver 2	All Other Transceivers
TTXLEMC (octet clks) 1	28	24
TTXOUT	TTXLEMC + GTdelay 3	TTXLEMC + GTdelay 3
TTXIN	0	0

¹ Latency values are given in 8b10b octet clocks. See TX End to End Latency for detailed use.

² When using Versal adaptive SoC GTME5 transceivers, there is an additional latency through the receive data path because the 8B10B encoding function is performed external to the GT Quad/GT Wizard subsystem.

³ For more information on GT latency, see GT documentation.

Table: 64B66B Transmit Data Path Latency Through JESD204C

	GTME5 Transceiver 2		All Other Transceivers
	With FEC	Without FEC	With FEC	Without FEC
TTXLEMC (core clks) 1	16 +/-1 3	14 +/-1 3	8	6
TTXOUT	TTXLEMC + GTdelay 4	TTXLEMC + GTdelay 4	TTXLEMC + GTdelay 4	TTXLEMC + GTdelay 4
TTXIN	0	0	0	0

¹ Latency values are given in core clock cycles. See TX End to End Latency for detailed use.

² When using Versal adaptive SoC GTME5 transceivers there is an additional latency through the receive data path because the 64b66b encoding function is performed external to the GT Quad/GT Wizard subsystem.

³ When using Versal adaptive SoC GTME5 transceivers, there is an additional +/- 1 clock cycle of uncertainty due to the clock crossing from the tx_core_clk to the txusrclk within the 64B66B encoder gearbox.

⁴ For more information on GT latency, see GT documentation.

TX End to End Latency

Overall latency in a JESD204C system requires consideration of the various sources of fixed and variable latencies across the link.

8B10B Line Coding

Core Timing

The key parameters of the FPGA transmitter required to calculate end to end latency are:

1. The fixed delay from SYSREF to LMFC (TTXLMFc)
2. The fixed delay from AXI input to LMFC (TTXIN)
3. The delay from LMFC to JESD204C serial output (TTXOUT)

The delay from SYSREF to LMFC and AXI data in to LMFC must be fixed for a Subclass 1 device but the delay from LMFC to JESD204C serial data out can vary because it is compensated for in the receiver during alignment to LMFC. See the following figure.

Figure: FPGA TX Timing

DAC Timing

The key parameters of the DAC receiver required to calculate end to end latency are:

1. The fixed delay from SYSREF to LMFC (TRXLMFc)
2. The delay from JESD204C input to LMFC (TRXIN)
3. The fixed delay from LMFC to analog output (TRXOUT)

The delay from SYSREF to LMFC and from LMFC to output must be fixed for a Subclass 1device but the delay from JESD204C serial data in to LMFC can vary as the receiver buffer compensates for variations in end to end latency. See the following figure.

Figure: DAC RX Timing

Calculating End to End Latency

The end to end latency is always fixed and made up of a multiple number of LMFC periods plus the fixed TX and RX delays. To calculate the end to end latency, use the following steps, referring to the following figure.

Figure: End to End Latency

Step 1: Determine How Many LMFC Periods are Required (N)

The delay between LMFC at TX and LMFC at RX (T) is an integer number (N) of LMFC periods adjusted by the internal delays from SYSREF to LMFC of TX and RX:

T = N * LMFC - TTXLMFc + TRXLMFc

To ensure the overall propagation delay is constant between system restarts, the maximum propagation delay must be less than T plus one LMFC period:

(TWIRE(max) + TRXIN(max) + TTXOUT(max)) < T + LMFC

The minimum propagation delay must also be > T:

(TWIRE(min) + TRXIN(min) + TTXOUT(min)) > T

Substituting (N * LMFC - TTXLMFc + TRXLMFc) for T gives:

(TWIRE(max) + TRXIN(max) + TTXOUT(max)) < ((N + 1) * LMFC - TTXLMFc + TRXLMFc)

(TWIRE(min) + TRXIN(min) + TTXOUT(min)) > (N * LMFC - TTXLMFc + TRXLMFc)

It is possible that no valid value for N can be found if the received data arrives close to an RX LMFC boundary and the variation in the link causes it to fall just before or just after the boundary after resetting the system. This would be seen as a jump in latency of exactly one LMFC period between system restarts. If no valid value can be found for N then the SYSREF signals can be delayed relative to one another to move the RX LMFC boundary relative to the TX LMFC boundary. For each cycle of delay added to TX SYSREF add four to TTXLMFc. Additional delay can be added to the SYSREF processing in the JESD204C core to accomplish this; see Table 15.

Step 2: Calculate the End to End Latency Using N

The data is received after N LMFC periods and before N + 1 LMFC periods so the min deterministic latency is T plus one LMFC plus the fixed input delay at the FPGA and the fixed output delay at the DAC:

TLAT = (T + LMFC) + TTXIN + TRXOUT

Substituting (N * LMFC - TTXLMFc + TRXLMFc) for T gives:

TLAT = ((N * LMFC - TTXLMFc + TRXLMFc) + LMFC) + TRXOUT + TTXIN = (N + 1) * LMFC - TTXLMFc + TRXLMFc + TTXIN + TRXOUT

Example

Table: Example

JESD204C + GT Latency	Assume a DAC with Parameters	Assume
TTXLMFc = 24 bytes	TRXIN = 50 ± 2 bytes	TWIRE = 0
TTXOUT = 40 ± 2 bytes	TRXLMFc = 4 bytes	LMFC = 32 bytes
TTXIN = 0	TRXOUT = 20 bytes

(TTXOUT(max) + TWIRE(max) + TRXIN(max)) < ((N + 1) * LMFC - TTXLMFc + TRXLMFc) (TTXOUT(min) + TWIRE(min) + TRXIN(min)) > (N * LMFC - TTXLMFc + TRXLMFc)

(42 + 0 + 52) < ((N + 1) * 32 - 24 + 4) and (38 + 0 + 48) > (N * 32 - 24 + 4)

Try N = 3

94 < 108 and 86 > 76

N = 3 is OK, no need to skew SYSREF

The data is received after three LMFCs (N) and less than four LMFCs (N + 1), so the latency is 4 * LMFC plus fixed delays:

TLAT = T + TTXIN TLAT = (N + 1) * LMFC - TTXLMFc + TRXLMFc + TTXIN = 128 - 24 + 4 + 20 = 128 byte clock periods

Note: GT latency is not accounted for these calculations.

Transmitter Phase Adjustment for Subclass 2

The core provides ports to enable the alignment of the frame clock and LMFC internal to the FPGA to those of the DAC receiver. The required clock and LMFC phase adjustments are communicated to the DAC using the ADJCNT, ADJDIR and PHADJ values in the CTRL_RX_ILA_CFG6 register as detailed in Table 41. In Subclass 2 devices, the DAC receiver deasserts the SYNC~ signal on its internal LMFC boundary. At the FPGA transmitter it is the responsibility of the client logic to detect the deassertion of the SYNC~ signal and to compare its timing to that of the transmitter LMFC. If adjustment of the DAC LMFC phase is required, the client inputs the required adjustment step count to the ADJCNT register. The direction of the phase adjustment is input on ADJDIR and an adjustment request is signaled by the assertion of the PHADJ register. The values on the phase adjustment ports are embedded in bytes 1 and 2 of the ILA sequence that is sent to the DAC during link initialization. On the reception of the ILA, the DAC adjusts its LMFC phase by the step count value and sends back an error report with the new LMFC phase information. This process can be repeated until the LMFC at the DAC and the FPGA are aligned.

64B66B Line Coding

Core Timing

The key parameters of the FPGA transmitter required to calculate end to end latency are:

1. The fixed delay from SYSREF to LEMC (TTXLEMC)
2. The fixed delay from AXI input to LEMC (TTXIN)
3. The delay from LEMC to JESD204C serial output (TTXOUT)

The delay from SYSREF to LEMC and AXI data into LEMC must be fixed for a Subclass 1 device, but the delay from LEMC to JESD204C serial data out can vary because it is compensated for in the receiver during alignment to LEMC. See the following figure.

Figure: FPGA TX Timing

DAC Timing

The key parameters of the DAC receiver required to calculate end to end latency are:

1. The fixed delay from SYSREF to LEMC (TRXLEMC)
2. The delay from JESD204C input to LEMC (TRXIN)
3. The fixed delay from LEMC to analog output (TRXOUT)

The delay from SYSREF to LEMC and from LEMC to output must be fixed for a Subclass 1 device, but the delay from JESD204C serial data into LEMC can vary because the receiver buffer compensates for variations in end to end latency. See the following figure.

Figure: DAC RX Timing

Calculating End to End Latency

The end to end latency is always fixed and made up of one LEMC period plus the fixed TX and RX delays. To calculate the end to end latency, use the following steps, referring to the following figure.

Figure: End to End Latency

The delay between LEMC at TX and LEMC at RX (T) is the LEMC period adjusted by the internal delays from SYSREF to LEMC of TX and RX:

T = LEMC - TTXLEMC + TRXLEMC

To ensure the overall propagation delay is constant between system restarts, the maximum propagation delay must be less than T:

TTXOUT(max) + TWIRE(max) + TRXIN(max) < T

Substituting LEMC - TTXLEMC + TRXLEMC for T gives:

TTXOUT(max) + TWIRE(max) + TRXIN(max) < LEMC - TTXLEMC + TRXLEMC

Additional delay can be added to the SYSREF processing in the JESD204C core (see Table 15). For each cycle of delay added to TX SYSREF, add 1 to TTXLEMC.

The data is received after the fixed delays of TX and RX adjusted by the internal delays from SYSREF to LEMC of TX and RX. This value is also the minimum value for deterministic latency.

TLAT = TTXOUT(max) + TWIRE(max) + TRXIN(max) - TTXLEMC + TRXLEMC

Example

Table: Example

JESD204C + GT Latency	Assume a DAC with Parameters	Assume
TTXLEMC = 6 words	TRXIN = 12 ± 1 words	TWIRE = 0
TTXOUT = 14 ± 1 words	TRXLEMC = 1 word	LEMC = 64 words
TTXIN = 0	TRXOUT = 5 words

TTXOUT(max) + TWIRE(max) + TRXIN(max) < LEMC - TTXLEMC + TRXLEMC 15 + 0 + 13 < 64 - 6 + 1 28 < 59

The data is received after the fixed delays of TX and RX adjusted by the internal delays from SYSREF to LEMC of TX and RX.

TLAT = TTXOUT(max) + TWIRE(max) + TRXIN(max) - TTXLEMC + TRXLEMC TLAT = 15 + 0 + 13 - 6 + 1 TLAT = 23 clock cycles

Note: GT latency is not accounted for these calculations.