Introduction
The AMD LogiCORE™ IP JESD204C core implements a JESD204C compatible interface supporting line rates from 1 Gbps to 32.5 Gbps (the maximum line rate supported is dependent on the transceiver type and speed grade of the selected device). The JESD204C core can be configured to transmit or receive using either a 64B66B or 8B10B link layer. The JESD204C core is fully backwards compatible with JESD204B.
Features
- Designed to JEDEC® JESD204C.1 Standard
- Supports GTY, GTYP, and GTM (NRZ only) transceivers on AMD Versal™ adaptive SoCs
- Supports GTH and GTY transceivers on AMD UltraScale+™ and AMD UltraScale™ devices
- Supports up to eight lanes per core and greater number of lanes using multiple cores
- Supports 64B66B and 8B10B link layers
- Supports FEC Encoding (TX) and Decoding (RX) on the 64B66B link layer
- Supports CRC-12, CMD and FEC meta data modes on the 64B66B link layer
- Supports subclass 0 and 1 on the 64B66B link layer and Subclass 0,1, and 2 on the 8B10B link layer
- Provides physical and data link layer functions when used with the Versal Adaptive SoC Transceiver Wizard or GT Wizard subsystem and the JESD204_PHY core for UltraScale and UltraScale+ devices
note
The Versal Adaptive SoC Transceiver Wizard/GT Wizard subsystem is used directly by the JESD204C core and the JESD204_PHY is no longer required.
- AXI4-Lite configuration interface
- AXI4-Stream Data and Command interfaces
- Supports Transceiver sharing between TX and RX cores using the JESD204_PHY core or Versal Adaptive SoC Transceiver Wizard/GT Wizard subsystem
IP Facts
| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family1 | Versal adaptive SoCs, UltraScale+, UltraScale |
| Supported User Interfaces | AXI4-Lite, AXI4-Stream |
| Resources | Performance and Resource Utilization web page |
| Provided with Core | |
| Design Files | Encrypted RTL |
| Example Design | Verilog |
| Test Bench | Verilog |
| Constraints File | XDC |
| Simulation Model | Verilog |
| Supported S/W Driver | N/A |
| Tested Design Flows 2 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 68804 |
Notes:
- For a complete list of supported devices, see the Vivado IP catalog.
- For the supported versions of third-party tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).