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RX Core

RX Core​

System Signals​

rx_core_clk​

  • Interface: System, s_axis_rx, s_axis_rx_cmd
  • I/O: I
  • Description: Core logic clock input.
    • Frequency:
      • Serial line rate / 66 (for 64B66B linecoding)
      • Serial line rate / 40 (for 8B10B linecoding)

rx_core_reset​

  • Interface: System
  • I/O: I
  • Description: Core asynchronous logic reset active-High.

rx_aresetn​

  • Interface: s_axis_rx, s_axis_rx_cmd
  • I/O: O
  • Description: AXI4-Stream interface reset. Active-Low. Associated with both data and command interfaces.

s_axi_aclk​

  • Interface: s_axi
  • I/O: I
  • Description: AXI4-Lite clock input.

s_axi_aresetn​

  • Interface: s_axi
  • I/O: I
  • Description: AXI4-Lite reset input. Active-Low.

s_axi*​

  • Interface: s_axi
  • I/O: I
  • Description: See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037) for a description of AXI4 signals.

irq​

  • Interface: System
  • I/O: O
  • Description: System interrupt output.

rx_sysref​

  • Interface: System
  • I/O: I
  • Description: SYSREF input. When Subclass 1 mode is selected, this signal is required and used by the core to set the phase of the local extended multi-block clock. This SYSREF signal must be generated synchronous to the core clock. This input should be driven from an external device generating SYSREF for both TX and RX on a link.

rx_sync​

  • Interface: System
  • I/O: O
  • Description: Sync signal. The sync signal is defined as an active-Low sync request signal by JESD204, so this signal is Low until comma alignment is completed and High to indicate the receiver is ready for ILA and normal data. This signal is only available when the core is generated with 8B10B linecoding selected.

encommaalign​

  • Interface: System
  • I/O: O
  • Description: Enable/disable 8B10B comma alignment logic within the JESD204_PHY or the Versal adaptive SoC (excluding GTM). This port should be connected to the Versal Adaptive SoC GT Quad/GT Wizard subsystem as follows:
    • JESD Channel 0: GPI[8]
    • JESD Channel 1: GPI[9]
    • JESD Channel 2: GPI[10]
    • JESD Channel 3: GPI[11]
  • This signal is only available when the core is generated with 8B10B linecoding selected and is N/A for Versal Adaptive SoC GTM designs.

Versal Adaptive SoCs​

gt_powergood1​

  • Interface: System
  • I/O: I
  • Description: This active-High signal from Versal Adaptive SoC Transceiver indicates when the GT clocking resources have completed power up.

rxusrclk1​

  • Interface: System
  • I/O: I
  • Description: Versal Adaptive SoC GTM 66-bit clock used for 64b66b decoder gearbox (GTM only).

reset_all1​

  • Interface: System
  • I/O: O
  • Description: Reset output to the gtwiz_versal subsystem reset controller. Resets RX PLL and datapath.

reset_rx_pll_and_datapath2​

  • Interface: System
  • I/O: O
  • Description: Reset output to the gtwiz_versal subsystem reset controller. Resets RX PLL and datapath.

reset_rx_datapath2​

  • Interface: System
  • I/O: O
  • Description: Reset output to the gtwiz_versal subsystem reset controller. Resets RX datapath only.

reset_rx_done2​

  • Interface: System
  • I/O: I
  • Description: Reset Done input from the gtwiz_versal subsystem reset controller. Active-High when RX reset sequence is complete.
note
  1. For an example of how to connect this port to the Versal Adaptive SoC GT Quad/GT Wizard subsystem, generate the example design.
  2. These ports are present only when you select the GT Wizard subsystem in JESD204C GUI.

UltraScale+/UltraScale Devices​

rx_reset_gt​

  • Interface: System
  • I/O: O
  • Description: JESD204_PHY RX datapath reset. Core output to reset the receive datapath in a connected JESD204_PHY. This must be connected to a JESD204_PHY.

rx_reset_done​

  • Interface: System
  • I/O: I
  • Description: JESD204_PHY RX reset done input. Indicates the JESD204_PHY has completed the receive reset process.
    For an example of how to connect this port to the JESD204_PHY or Versal adaptive SoC GT Quad/GT Wizard subsystem, generate the example design.

Versal Adaptive SoC GT RX Interface Ports​

chN_rxctrl0[15:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: RX Char is K from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxctrl1[15:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: RX Disparity Error from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxctrl2[7:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: RX Char is Comma from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxctrl3[7:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: Not In Table Error from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxdata[127:0]3​

  • Interface: GT_RX
  • I/O: I
  • Description: RX Data from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxdatavalid[1:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: Data Valid from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxgearboxslip​

  • Interface: GT_RX
  • I/O: O
  • Description: RX Gearbox Slip to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxheader[5:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: Header from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxheadervalid[1:0]​

  • Interface: GT_RX
  • I/O: I
  • Description: RX Header Valid from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxlpmen​

  • Interface: GT_RX
  • I/O: O
  • Description: RX LPM Mode Enable to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxmstdatapathreset4​

  • Interface: GT_RX
  • I/O: O
  • Description: Master Datapath only Reset sequence start to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxmstreset4​

  • Interface: GT_RX
  • I/O: O
  • Description: Master Reset sequence start to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxmstresetdone4​

  • Interface: GT_RX
  • I/O: I
  • Description: Master Reset sequence Done to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxpd[1:0]​

  • Interface: GT_RX
  • I/O: O
  • Description: Power Down to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxpmaresetdone4​

  • Interface: GT_RX
  • I/O: I
  • Description: PMA Reset Done from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxpolarity​

  • Interface: GT_RX
  • I/O: O
  • Description: Polarity control to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxprbscntreset​

  • Interface: GT_RX
  • I/O: O
  • Description: RX PRBS Counter Reset to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxprbserr​

  • Interface: GT_RX
  • I/O: I
  • Description: RX PRBS Error from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxprbslocked​

  • Interface: GT_RX
  • I/O: I
  • Description: RX PRBS Locked from the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxprbssel[3:0]​

  • Interface: GT_RX
  • I/O: O
  • Description: RX PRBS Select to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN_rxrate[7:0]​

  • Interface: GT_RX
  • I/O: O
  • Description: RX Line Rate to the Versal Adaptive SoC Transceiver. N = Lanes - 1

chN-rxusererdy4​

  • Interface: GT_RX
  • I/O: O
  • Description: RX User clocks stable to the Versal Adaptive SoC Transceiver. N = Lanes - 1
note
  1. JESD204C only uses the above subset of the available signals on the Versal Adaptive SoC Transceiver Rx_GT_IP_Interface. For further details, see Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).
  2. The ports mentioned here are connected between the JESD204 core and the Versal Adaptive SoC Transceiver using Block Automation when legacy GT Wizard is selected in JESD204C GUI. For more information, see Design Flow Steps. When you select the GT Wizard subsystem in JESD204C GUI, Block Automation is not available. The RX_GT_IP_Interface must be manually connected to the GT Wizard subsystem.
  3. In Versal Adaptive SoC GTM designs this port is [255:0].
  4. These ports are present only when you select the GT Wizard subsystem in JESD204C GUI.

JESD204_PHY Interface Ports for UltraScale+/UltraScale Devices​

gtN_rxdata[63:0]​

  • Interface: PHY
  • I/O: I
  • Description: RX data from JESD204 PHY. N = Lanes - 1

gtN_rxheader[1:0]​

  • Interface: PHY
  • I/O: I
  • Description: RX header from JESD204 PHY. N = Lanes - 1

gtN_misalign​

  • Interface: PHY
  • I/O: I
  • Description: Signal from JESD204 PHY to indicate a misaligned sync header was detected. N = Lanes - 1

gtN_block_sync​

  • Interface: PHY
  • I/O: I
  • Description: Signal from JESD204 PHY to indicate block sync status. N = Lanes - 1

gtN_rxcharisk[3:0]​

  • Interface: PHY
  • I/O: I
  • Description: RX Char is K from JESD204 PHY. N = Lanes - 1

gtN_rxdisperr[3:0]​

  • Interface: PHY
  • I/O: I
  • Description: RX Disparity Error from JESD204 PHY. N = Lanes - 1

gtN_notintable[3:0]​

  • Interface: PHY
  • I/O: I
  • Description: RX Not In Table Error from JESD204 PHY. N = Lanes - 1

Receive Interface (64B66B Linecoding Only)​

rx_tdata[(64*N)-1:0]​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Receive data output. N = Lanes

rx_tvalid​

  • Interface: m_axis_rx
  • I/O: O
  • Description: AXI4-Stream tvalid.

rx_soemb​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Start of extended multi-block boundary indication. Set to 1 to indicate tx_tdata in the following clock cycle is the start of an extended multi-block.

rx_emb_err​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Extended Multi-block Error. Set to 1 on the last block of an extended multi-block if a multi-block alignment error was detected.

rx_crc_err​

  • Interface: m_axis_rx
  • I/O: O
  • Description: CRC error. Set to 1 on the last block of a multi-block if a CRC or Uncorrectable FEC error was detected within the multi-block.

rx_cmd_tdata[(32*N)-1:0]​

  • Interface: m_axis_rx_cmd
  • I/O: O
  • Description: Receive Cmd interface. N = Lanes. For Meta mode = CRC, Cmd payload is bits [6:0] with bits [31:7] set to Zero. For Meta mode = CMD, Cmd payload is [18:0] with bits [31:19] set to Zero.

rx_cmd_tvalid​

  • Interface: m_axis_rx_cmd
  • I/O: O
  • Description: AXI4-Stream tvalid. rx_cmd_tvalid will be set for one cycle every multi-block to output the Cmd word.

rx_cmd_tready​

  • Interface: m_axis_rx_cmd
  • I/O: I
  • Description: AXI4-Stream tready.

rx_cmd_tuser[N:0]​

  • Interface: m_axis_rx_cmd
  • I/O: O
  • Description: AXI4-Stream tuser. N = Lanes - 1.
    The tuser data bits are used to signal that a Multiblock Alignment error was detected in the previous multiblock of the associated lane. This might mean the CMD data is invalid.

Receive Interface (8B10B Linecoding Only)​

rx_tdata[(32*N)-1:0]​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Receive data output. N = Lanes

rx_tvalid​

  • Interface: m_axis_rx
  • I/O: O
  • Description: AXI4-Stream tvalid.

rx_sof[3:0]​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Start of frame boundary indication. The position of the first byte of each frame in tdata. Bit 3 of the error signal corresponds to the most significant byte of lane 4 and bit 0 of the error signal corresponding to the least significant byte of lane 1. This signal is synchronous to rx_core_clk and output in the cycle before the data in the same way as rx_sof.

rx_somf[3:0]​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Start of multiframe boundary indication. The position of the first byte of each multiframe is encoded in the same way as rx_sof.

rx_frm_err[3:0]​

  • Interface: m_axis_rx
  • I/O: O
  • Description: Error in byte.
    JESD204 specifies that data must be replicated from the previous frame if certain errors occur. The core does not buffer the previous frame. You can choose to implement a frame buffer or use a buffer elsewhere in the system to perform this function if required.
    The rx_frm_err signal indicates that a single byte error exists in the data stream. There is one bit for each byte of each AXI4-Stream. For example, a four lane interface has four 32-bit AXI4-Streams, the error signal is 16 bits wide with bit 15 of the error signal corresponding to the most significant byte of lane 4 and bit 0 of the error signal corresponding to the least significant byte of lane 1.
    This signal is synchronous to rx_core_clk and output in the cycle before the data in the same way as rx_sof.>