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5 Attribute, Port and Register List

The TI-204c JESD IP is built using two primary components

  • The encrypted System Verilog (RTL) core of the IP. This is generic and includes all the functionality of the JESD data link layer. The core of the IP is non-specific and can be synthesized for any FPGA using the Vivado tool flow.
  • The non-encrypted Transceiver Wrapper logic that instantiates the Transceiver IP. The Transceiver IP is extremely specific to the FPGA part chosen to the application and must be generated using the Vivado Transceiver Wizard. This wrapper is instantiated inside the IP core, and can be customized by the designer (if the transceiver is enhanced for functionality beyond that required by the core IP).

This section describes the Attribute, Port and Register lists of the top level TI204c-IP.

5.3 Register list​

The TI204c-IP does not contain any registers, and hence does not implement a programming read/write interface. All the status and error signals are available as ports, ensuring minimal latency between the detection of an event and its update at the output of the IP. This latency is typically higher if the status is updated into a register that needs to be accessed by the application.

Any port that is tied to a static value or not connected to the application upstream/downstream will automatically result in the associated IP logic getting optimized during synthesis. This guarantees that the IP has the minimal required impact on the FPGA logic and routing resources.