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3 Design Flow Methodology

The JESD protocol is fairly complex owing to the high data rates and multiple layers involved. As a result, it brings with it challenges in the areas of design, implementation and debug. This can often cause extended cycle times, either for system development and time to market, or for failure analysis of existing solutions. In some cases, engineers may choose an LVDS interface based solution, trading off perceived JESD bring-up effort vs board cost and complexity.

The TI 204c FPGA IP has been designed to minimize the overall time and effort required to implement a working link between a TI ADC and a host/application FPGA. This is accomplished by keeping most of the complexity of the protocol ‘under the hood’, requiring the user to provide a few configuration parameters that will optimize the IP for the JESD application being targeted. In addition, a generic reference design is provided as a starting point, which can then be modified to meet the actual application needs.

Design engineers using the TI204c IP are encouraged to follow the flow specified below. This will ensure a smooth and minimally time intensive transition from specifications to the final working JESD application. The steps are:

  1. Determine the JESD link parameters needed by your application
    • Please refer to the JESD specifications of the chosen TI data converter for more information
  2. Determine the FPGA of choice
    • The FPGA selected should support the lane rates and transceiver counts required by the application
  3. You will be provided a reference design that is customized for your application needs and targeted for a Xilinx development kit or a prototype FPGA boad. You can use it as a starting point to carry out the following (if necessary):
    • Further customize the MGT transceiver block or re-map it for a different FPGA
    • Further customize the JESD IP
    • Edit the reference design to include logic specific to your application
    • Edit/customize the synthesis and place-and-route constraints
  4. Run the Vivado design flow to generate the bitfile for system bring-up and debug

The JESD link parameters should be determined based on the application needs and the JESD modes supported by the data converter.

  • Sampling rate (Fs). This is the primary constraint of any data acquisition system. For a given link, a higher Fs will result in a higher data throughput requirement on the link
    • Please refer to the JMODE/LMFS mode tables of the data converter datasheet to determine the Lane Rate corresponding to a given Fs.
  • Number of lanes (L). Choosing a mode where a channel’s data is divided over multiple lanes will help reduce the overall line rate. The trade-off is higher routing resources on the board and more I/O resources on the FPGA
  • Encoding protocol. The JESD standard offers two encoding protocols:
    • The 8b/10b protocol guarantees DC balancing on the traces and also includes a number of error checking mechanisms for bit errors. However, it has two limitations
      • There is a 20% bandwidth loss, as each 8bit code is converted to a 10bit representation. This results in a greater line rate requirement
      • The transceivers are limited to approximately 16.375Gbps when carrying out 8b/10b decoding. This encoding is not recommended above 12.5Gbps, especially if DFE is enabled at the receiver.
    • The 64b/66b protocol has a much smaller overhead and supports lane rates of up to 32Gbps. However, this is a relatively new inclusion in the JESD standard, so the number of data converters (and JESD modes within converters) supporting this mode may be less than the corresponding support for 8b/10b.
  • Link synchronization and/or deterministic latency
    • In certain applications, there may be a need to synchronize multiple links or multiple devices connected to one FPGA
    • In other applications there may be one or more synchronized links, but there is an additional requirement that the end to end delay (front end of ADC to data output of the receive JESD IP in the FPGA) should remain defined and constant across all possible variations and across power cycles.

Once the JESD link modes have been determined, the designer should have the following parameters defined:

  • L : number of lanes
  • LR : Lane rate (Gbps)
  • Encoding
    • 8b/10b requires the following additional parameters
      • F: Number of octets per frame
      • K: Number of frames per multiframe
    • 64b/66b requires the following
      • E: Number of multi-blocks in an extended multi-block

3.2 Determining the FPGA of choice​

Once the JESD link parameters have been defined, choosing the FPGA will depend on a number of factors:

  • The FPGA must support as many transceivers as the number of lanes required in the link(s)
  • The FPGA transceivers must support the targeted line rate
  • The transceivers must support the clock buffering and routing constraints imposed by the board level connections (which are usually optimized to keep costs low)
  • The FPGA fabric must support adequate resources to accommodate both the JESD IP and the application logic (without over-burdening the routing, congestion and timing constraints that the tool needs to honor).

The UltraScale, UltraScale+ and 7000 series of families contain a variety of transceiver classes, named as GTY, GTH, GTX and GTP. The TI-204c IP is compatible with all of these classes, and generates the signals necessary to interface with and control the transceiver operation.

The TI204c-IP is compatible with the following Xilinx FPGAs.

  • Xilinx Virtex™ UltraScale™ and UltraScale+™
  • Xilinx Kintex™ UltraScale and UltraScale+
  • Xilinx Zynq™ UltraScale+ and Zynq UltraScale+ (Auto)
  • Xilinx Artix™ 7 and Artix 7 (Auto)
  • Xilinx Virtex 7
  • Xilinx Kintex 7 and Kintex 7 (Auto)
  • Xilinx Zynq7000 and Zynq7000 (Auto)

Note: Pease refer to the official TI204c-IP page for the latest list of supported FPGAs, as it may get updated over time.