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5.2 Port List

The following table lists the ports available on the IP. The tables have been divided to group signals of a common functionality together.

Top-Level Ports​

master_reset_n​

Width: 1
Dir: IN
Clock Domain: Async

  • Master reset for the entire IP (active low). This resets both the transceiver as well as the Rx and Tx datapaths in the JESD IP.
    Must be held at ‘0’ on power-up or after a link loss. This will keep all the IP components in reset, and should be set to ‘1’ after all clocks supplied to this IP have reached a stable frequency

mgt_freerun_clock​

Width: 1
Dir: IN
Clock Domain: NA

  • Free-running clock input to the MGT transceiver. Used for initialization and reset control of the MGT.
    Refer to the GT wizard to ensure that its frequency matches what was set while generating the MGT IP

mgt_refclk_p​

Width: NUM_REFCLK_BUFFERS
Dir: IN
Clock Domain: NA

  • Differential reference clock inputs to the MGT transceiver

mgt_refclk_n​

Width: NUM_REFCLK_BUFFERS
Dir: IN
Clock Domain: NA

  • Differential reference clock inputs to the MGT transceiver

mgt_gpio_in​

Width: MGT_GPIO_IN_WIDTH
Dir: IN
Clock Domain: NA

  • User GP input bus. This is the MGT transceiver related general purpose IN port

mgt_gpio_out​

Width: MGT_GPIO_OUT_WIDTH
Dir: OUT
Clock Domain: NA

  • User GP output bus. This is the MGT transceiver related general purpose OUT port

qpll0_locked​

Width: NUM_QUADS
Dir: OUT
Clock Domain: mgt_freerun_clock

  • GTY and GTH transceivers : QPLL0 locked status
  • GTX transceivers : QPLL locked status
  • GTP transceivers : PLL0 locked status

qpll1_locked​

Width: NUM_QUADS
Dir: OUT
Clock Domain: mgt_freerun_clock

  • GTY and GTH transceivers : QPLL1 locked status
  • GTX transceivers : QPLL locked status
  • GTP transceivers : PLL1 locked status

cpll_locked​

Width: NUM_RX_LANES/NUM_TX_LANES
Dir: OUT
Clock Domain: mgt_freerun_clock

  • Locked status of the individual lane(channel) PLLs

mgt_lane_rxp​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: NA

  • Serial Data In port of the Transceiver Rx channels

mgt_lane_rxn​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: NA

  • Serial Data In port of the Transceiver Tx channels

mgt_lane_txp​

Width: NUM_TX_LANES
Dir: OUT
Clock Domain: NA

  • Serial Data Out port of the Transceiver Tx channels

mgt_lane_txn​

Width: NUM_TX_LANES
Dir: OUT
Clock Domain: NA

  • Serial Clock Out port of the Transceiver Tx channels

Rx IP Clocks and Reset Ports​

rx_sys_clock​

Width: 1
Dir: IN
Clock Domain: NA

  • This is the system clock of the Rx IP. All output data and side-band signals are synchronous to this clock.
    Note: The frequency of this clock must be equal to or greater than the data generation rate of the Rx IP (to avoid data loss).
    The frequency of this clock is derived as follows:
    • 8b10b modes:
      • If RX_LN_DATA_WIDTH = 32, Fsysclk >= LineRate/40
      • If RX_LN_DATA_WIDTH = 64, Fsysclk >= LineRate/80
    • 64b66b modes:
      • If RX_LN_DATA_WIDTH = 32, Fsysclk >= LineRate/33
      • If RX_LN_DATA_WIDTH = 64, Fsysclk >= LineRate/66
      • If RX_LN_DATA_WIDTH = 128, Fsysclk >= LineRate/132

rx_sync_reset​

Width: 1
Dir: IN
Clock Domain: rx_sys_clock

  • Synchronous reset for the Rx IP. When set to 1, it resets only the Data Link Layer of the Rx IP.
    Note: after power-up or a link loss event, it is recommended to hold rx_sync_reset at 1 after master_reset_n is deactivated from 1 to 0. The rx_sync_reset should be held active until the PLL lock signals of the transceiver have transitioned to 1.
    Note: the rx_sync_reset can be independently used for a quick clear and resync of all the lanes in the IP (without the additional latency of re-initializing the analog components in the transceiver).

mgt_rx_usrclk2​

Width: 1
Dir: OUT
Clock Domain: NA

  • This is the usrclk2 clock generated by the transceiver. The frequency of this clock is derived as follows:
    • 8b10b modes:
      • If RX_LN_DATA_WIDTH = 32, Fusrclk2 = LineRate/40
      • If RX_LN_DATA_WIDTH = 64, Fusrclk2 = LineRate/80
    • 64b66b modes:
      • If RX_LN_DATA_WIDTH = 32, Fusrclk2 = LineRate/33
      • If RX_LN_DATA_WIDTH = 64, Fusrclk2 = LineRate/66
      • If RX_LN_DATA_WIDTH = 128, Fusrclk2 = LineRate/132

Rx IP Status and Control Ports​

cfg_rx_lane_map​

Width: Array: NUM_RX_LANES values of width RX_LN_IDX_WIDTH
Dir: IN
Clock Domain: NA (False Path)

  • This array defines the mapping of the ADC data lanes to the Rx input lanes of the FPGA transceiver.
    Note: For an N lane transceiver, this port must be driven with N unique values from 0 through N-1
    Note: For a Tx only IP, the values can all be driven to ‘h0

cfg_rx_lane_polarity​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: NA (False Path)

  • Polarity control for ADC lanes connected to the transceiver's Rx ports. The functionality of each bit is as follows:
    • 0 : Respective lane of the ADC is connected to the FPGA using matched polarity
    • 1 : Respective lane of the ADC is connected to the FPGA through a polarity inversion

cfg_rx_lane_enable​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: NA (False Path)

  • Enable control for ADC lanes connected to the transceiver's Rx ports. The functionality of each bit is as follows:
    • 0 : Respective lane is enabled in the Rx IP
    • 1 : Respective lane is enabled in the Rx IP
      Note: This port should be tied to all 1s. However, it can be used to isolate and debug lane related issues if necessary.

rx_all_lanes_locked​

Width: 1
Dir: OUT
Clock Domain: rx_sys_clock

  • When 1, indicates that all the lanes in the Rx IP have locked to the character / block boundaries embedded in their respective data streams from the transmitter.
    • 8b/10b mode: Indicates that all lanes have aligned to the K char boundaries during the CGS phase.
    • 64b/66b mode: Indicates that all lanes have aligned to the multi-block and extended multi-block boundaries in the data stream.
      Note: This signal can be used to detect and synchronize the release of Rx data lanes if there are multiple JESD Rx IP's in the FPGA. In the case of single IP designs, this signal can be left unused.

rx_release_all_lanes​

Width: 1
Dir: IN
Clock Domain: rx_sys_clock

  • When set to 0, this holds the Rx IP from releasing the data lanes.
    When set to 1, this initiates the lane release sequence of the Rx IP on the subsequent LEMC / LMFC event, thus allowing the control of multiple Rx IP's to release in a synchronized manner.
    Note: In the case of multi JESD IP designs, this signal should transition from 0 to 1 after rx_all_lanes_locked output of all IP's has transitioned from 0 to 1.
    Note: In case there is only one Rx IP in the design, this signal can be tied to 1.
    Note: This signal does not guarantee deterministic latency. It only guarantees a synchronized release of all lanes across multiple JESD Rx IPs in the FPGA.

rx_lane_data​

Width: Array: NUM_RX_LANES of width RX_LN_DATA_WIDTH
Dir: OUT
Clock Domain: rx_sys_clock

  • Output data buses of the Rx IP. There is one output bus per transceiver lane.
    note

    All the lanes within one JESD Rx will release in a synchronized manner.

rx_lane_valid​

Width: 1
Dir: OUT
Clock Domain: rx_sys_clock

  • Data valid signal for the output lane data and sideband signals of the Rx IP.
    • When 1, it indicates that the new data and sideband signals are valid and can be used by the downstream logic for processing.
    • When 0, the last valid values of the data and sideband signals will be held. These values should be discarded from downstream processing.
      The rx_lane_valid signal will intermittently transition from 1 to 0 if the frequency of rx_sys_clock (Fsysclk) is greater than the minimum value described in this table. If the Fsysclk is maintained at the minimum value, the data valid will always remain 1 after the lanes have released.

rx_lane_buffer_overflow​

Width: NUM_RX_LANES
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • When set to 1, this indicates that the data buffer of the respective lane has encountered an overflow, thereby resulting in a loss of data.
    Note: This is a sticky flag and will be cleared only by a sync reset or master reset, as it requires a re-sync of all the lanes of the Rx IP before samples can reliably be extracted from the rx_lane_data outputs of the Rx IP.

rx_lane_samples​

Width: 3D array: NUM_RX_LANES arrays, each containing SAMPLES_PER_CYCLE_PER_LANE values of ADC_RES
Dir: OUT
Clock Domain: rx_sys_clock

  • Output of the internal transport layer of the JESD Rx IP. This consists of the lane data, sorted into separate samples and packed into the required number of samples per cycle.
    note
    • This is an advanced feature of the JESD Rx IP and will be provided with the customized reference design.
    • The embedded transport layer may not be available for all JESD modes of the various data converters from TI.
    • The embedded transport layer may add a latency between the lane data and the final output samples. If this latency is not desirable, the designer is encourage to create customized logic to map the lane data to samples.

rx_lane_samples_valid​

Width: NUM_RX_LANES
Dir: OUT
Clock Domain: rx_sys_clock

  • When 1, indicates that the values on the rx_lane_samples bus are valid.
    note

    All the bits of the rx_lane_samples_valid output will transition to 0 to 1 simultaneously. If this is not the case, it indicates that samples from one (or more) of the lanes may be out of sync with the rest.

rx_sync_n​

Width: 1
Dir: OUT
Clock Domain: rx_sys_clock

  • SYNCn output of the JESD Rx IP. This is valid only in 8b/10b mode.

cfg_rx_scrambling_enabled​

Width: 1
Dir: IN
Clock Domain: NA (false path)

  • When 1 enables the de-scrambling feature of the Rx IP.

rx_lane_configuration_data​

Width: Array: NUM_RX_LANES of 112 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • These are the 14 concatenated ILAS configuration octets received on each lane of the Rx IP.
    The octets are arranged in increasing order in the 112 bit bus, with octet 0 at bits 7:0 and octet 13 at bits 111:104.
    Note: The value of this output is updated just once after the ILAS phase, and retained until the next reset/re-sync event.

rx_lane_start_of_frame​

Width: Array: NUM_RX_LANES of RX_LN_DATA_WIDTH/8 bits each
Dir: OUT
Clock Domain: rx_sys_clock

  • This output accompanies the rx_lane_data and qualifies the corresponding byte as a start of frame delimiter. This value is valid only when rx_lane_data_valid is 1.

rx_lane_start_of_multiframe​

Width: Array: NUM_RX_LANES of RX_LN_DATA_WIDTH/8 bits each
Dir: OUT
Clock Domain: rx_sys_clock

  • This output accompanies the rx_lane_data and qualifies the corresponding byte as a start of multi-frame delimiter.
    This value is valid only when rx_lane_data_valid is 1.

rx_lane_start_of_mblock​

Width: NUM_RX_LANES
Dir: OUT
Clock Domain: rx_sys_clock

  • This output accompanies the rx_lane_data and qualifies the most significant byte of the current rx_lane_data bus as a start of multi-block delimiter.
    This value is valid only when rx_lane_data_valid is 1.

rx_lane_start_of_emblock​

Width: NUM_RX_LANES
Dir: OUT
Clock Domain: rx_sys_clock

  • This output accompanies the rx_lane_data and qualifies the most significant byte of the current rx_lane_data bus as a start of extended multi-block delimiter.
    This value is valid only when rx_lane_data_valid is 1.

rx_lane_crc_error​

Width: NUM_RX_LANES
Dir: OUT
Clock Domain: rx_sys_clock

  • This output accompanies the rx_lane_data and indicates a CRC comparison error on the last received CRC value in the header stream and the computed CRC of the previous multi-block.

rx_clr_all_err_count​

Width: 1
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, this will clear all the independent 8b/10b and 64b/66b error counts exported by the IP.

Rx IP Error Counters​

rx_lane_invalid_somf_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of invalid 'start of multi-frame' events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_invalid_somf_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_invalid_somf_err_count value for the respective lane.

rx_lane_invalid_eomf_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of invalid 'end of multi-frame' events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_invalid_eomf_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_invalid_eomf_err_count value for the respective lane.

rx_lane_invalid_eof_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of invalid 'end of frame' events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_invalid_eof_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_invalid_eof_err_count value for the respective lane.

rx_lane_notintable_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of 'not in table' events detected in the receive stream for the respective lane. Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_notintable_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_notintable_err_count value for the respective lane.

rx_lane_disp_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of '8b/10b running disparity error' events detected in the receive stream for the respective lane. Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_disp_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_disp_err_count value for the respective lane.

rx_lane_invalid_header_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of 'invalid header error' events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_invalid_header_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_invalid_header_err_count value for the respective lane.

rx_lane_eomb_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of out of position end of multi-block events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_eomb_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_eomb_err_count value for the respective lane.

rx_lane_eoemb_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of out of position end of extended multi-block events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_eoemb_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_eoemb_err_count value for the respective lane.

rx_lane_crc_mismatch_err_count​

Width: Array: NUM_RX_LANES of 4 bits each
Dir: OUT
Clock Domain: mgt_rx_usrclk2

  • Number of CRC mismatch events detected in the receive stream for the respective lane.
    Note: This will stop incrementing at the max value of 'hF.

rx_lane_clr_crc_mismatch_err_count​

Width: NUM_RX_LANES
Dir: IN
Clock Domain: mgt_rx_usrclk2

  • When set to 1, clears the rx_lane_crc_mismatch_err_count value for the respective lane.

Rx IP SYSREF and Alignment Ports​

rx_sysref​

Width: 1
Dir: IN
Clock Domain: rx_sys_clock

  • A positive edge detect on this signal is treated as a SYSREF event in the JESD Rx IP.

rx_lmfc_pulse​

Width: 1
Dir: OUT
Clock Domain: rx_sys_clock

  • Single cycle pulse, indicating an LMFC (multi-frame boundary) event in the JESD Rx IP.
    Note: This is applicable only in 8b/10b mode.

rx_lemc_pulse​

Width: 1
Dir: OUT
Clock Domain: rx_sys_clock

  • Single cycle pulse, indicating an LEMC (extended multi-block boundary) event in the JESD Rx IP.
    Note: This is applicable only in 64b/66b mode.

rx_sysref_realign_count​

Width: 4
Dir: OUT
Clock Domain: rx_sys_clock

  • Indicates the number of times a SYSREF event caused a re-alignment of the LMFC/LEMC timing in the JESD Rx IP (after the last reset event).
    This stops incrementing after a reaching a max value of 'hF.

rx_clr_sysref_realign_count​

Width: 1
Dir: IN
Clock Domain: rx_sys_clock

  • When 1, clears the rx_sysref_realign_count.

Rx IP Deterministic Latency Ports​

cfg_rx_det_latency_en​

Width: 1
Dir: IN
Clock Domain: NA (False Path)

  • Enable control for deterministic latency. The functionality of the bit is as follows:
    • 0: Rx IP lanes release together as soon as data is available in the buffer of each lane.
    • 1: Rx IP lanes release after data is available AND the cfg_rx_buffer_release_delay value is reached.

cfg_rx_buffer_release_delay​

Width: RX_RBD_COUNT_WIDTH
Dir: IN
Clock Domain: rx_sys_clock (false path)

  • Delay count value that is honored by the Rx IP before lanes are released.
    Note: This delay is ignored if deterministic latency has been disabled
    Note: If the value of this delay is set to 0, and deterministic latency has been enabled, then the Rx IP will release its lanes on the first available cycle when each lane’s data buffer has at least one entry.
    Note: The delay value is reflected in rx_sys_clock cycles

rx_lmfc_to_buffer_release_delay​

Width: RX_RBD_COUNT_WIDTH
Dir: OUT
Clock Domain: rx_sys_clock

  • Reflects the number of clock cycles taken by the IP to release its lanes in 8b/10b mode.
    Note: This count starts on the multi frame boundary after the IP has asserted its rx_all_lanes_locked signal AND the rx_release_all_lanes input is 1.
    Note: The delay is measured in rx_sys_clock cycles

rx_lemc_to_buffer_release_delay​

Width: RX_RBD_COUNT_WIDTH
Dir: OUT
Clock Domain: rx_sys_clock

  • Reflects the number of clock cycles taken by the IP to release its lanes in 64b/66b mode.
    Note: This count starts on the extended multi-block boundary after the IP has asserted its rx_all_lanes_locked signal AND the rx_release_all_lanes input is 1.
    Note: The delay is measured in rx_sys_clock cycles

Tx IP Clock and Reset Ports​

mgt_tx_usrclk2​

Width: 1
Dir: OUT
Clock Domain: NA

  • This is the usrclk2 clock generated by the transceiver. The frequency of this clock is derived as follows:
    • 8b10b modes:
      • If TX_LN_DATA_WIDTH = 32, Fusrclk2 = LineRate/40
      • If TX_LN_DATA_WIDTH = 64, Fusrclk2 = LineRate/80
    • 64b66b modes:
      • If TX_LN_DATA_WIDTH = 32, Fusrclk2 = LineRate/33
      • If TX_LN_DATA_WIDTH = 64, Fusrclk2 = LineRate/66
      • If TX_LN_DATA_WIDTH = 128, Fusrclk2 = LineRate/132

tx_sys_clock​

Width: 1
Dir: IN
Clock Domain: NA

  • This is the system clock of the Tx IP. All input data and output side-band signals are synchronous to this clock.
    Note: The frequency of this clock must be equal to the data consumption rate of the Tx IP (to avoid data loss).
    The frequency of this clock is derived as follows:
    • 8b10b modes:
      • If TX_LN_DATA_WIDTH = 32, Fsysclk = LineRate/40
      • If TX_LN_DATA_WIDTH = 64, Fsysclk = LineRate/80
    • 64b66b modes:
      • If TX_LN_DATA_WIDTH = 32, Fsysclk = LineRate/33
      • If TX_LN_DATA_WIDTH = 64, Fsysclk = LineRate/66
      • If TX_LN_DATA_WIDTH = 128, Fsysclk = LineRate/132

tx_sync_reset​

Width: 1
Dir: IN
Clock Domain: tx_sys_clock

  • Synchronous reset for the Tx IP. When set to 1, it resets only the Data Link Layer of the Tx IP.
    Note: after power-up or a link loss event, it is recommended to hold tx_sync_reset at 1 after master_reset_n is deactivated from 1 to 0. The rx_sync_reset should be held active until the PLL lock signals of the transceiver have transitioned to 1.
    Note: the tx_sync_reset can be independently used for a quick clear and resync of all the lanes in the IP (without the additional latency of re-initializing the analog components in the transceiver).

Tx IP Data Ports​

cfg_tx_lane_map​

Width: NUM_TX_LANES*3 bits (packed)
Dir: IN
Clock Domain: NA (False Path)

  • This array defines the mapping of the DAC data lanes to the Tx output lanes of the FPGA transceiver.
    Note: For an N lane transceiver, this port must be driven with N unique values from 0 through N-1
    Note: For an Rx only IP, the values can all be driven to ‘h0

cfg_tx_lane_polarity​

Width: NUM_TX_LANES
Dir: IN
Clock Domain: NA (False Path)

  • Polarity control for DAC lanes connected to the transceiver's Tx ports. The functionality of each bit is as follows:
    • 0 : Respective lane of the DAC is connected to the FPGA using matched polarity
    • 1 : Respective lane of the DAC is connected to the FPGA through a polarity inversion

cfg_tx_lane_enable​

Width: NUM_TX_LANES
Dir: IN
Clock Domain: NA (False Path)

  • Enable control for DAC lanes connected to the transceiver's Tx ports. The functionality of each bit is as follows:
    • 0: Respective lane is enabled in the Tx IP
    • 1: Respective lane is enabled in the Tx IP
      Note: This port should be tied to all 1s. However, it can be used to isolate and debug lane related issues if necessary.

tx_lane_data​

Width: Array: NUM_TX_LANES of width TX_LN_DATA_WIDTH
Dir: IN
Clock Domain: tx_sys_clock

  • Input data buses of the Tx IP. There is one input bus per transceiver lane.
    Note: All the lanes within one JESD Tx will consume data in a synchronized manner.

tx_lane_data_ready​

Width: 1
Dir: OUT
Clock Domain: tx_sys_clock

  • Data ready signal for the input lane data and output sideband signals of the Tx IP.
    • When 1, it indicates that the sideband signals are valid and that the upstream logic should drive the relevant data on the tx_lane_data inputs.

tx_sync_n​

Width: 1
Dir: IN
Clock Domain: tx_sys_clock (false path)

  • SYNCn input of the JESD Tx IP.
    Note: This signal is internally synchronized and sampled by the IP logic.

cfg_tx_scrambling_enabled​

Width: 1
Dir: IN
Clock Domain: NA (false path)

  • When 1 enables the data scrambling feature of the Tx IP.
    Note: This must be tied to 1. The current version of the TI204c IP does not support 8b/10b Tx mode with scrambling disabled.

cfg_tx_ilas_test_mode​

Width: 1
Dir: IN
Clock Domain: NA (false path)

  • When 1 configures the JESD Tx IP to continuously transmit the ILA sequence.

Tx IP Sideband Signals​

tx_lane_start_of_frame​

Width: TX_LN_DATA_WIDTH/8
Dir: OUT
Clock Domain: tx_sys_clock

  • This output accompanies and qualifies the corresponding byte of the tx_lane_data as a start of frame delimiter.

tx_lane_start_of_multiframe​

Width: TX_LN_DATA_WIDTH/8
Dir: OUT
Clock Domain: tx_sys_clock

  • This output accompanies and qualifies the corresponding byte of the tx_lane_data as a start of multi-frame delimiter.

tx_lane_start_of_mblock​

Width: NUM_TX_LANES
Dir: OUT
Clock Domain: tx_sys_clock

  • This output accompanies and qualifies the most significant byte of each lane of the current tx_lane_data bus as a start of multi-block delimiter.

tx_lane_start_of_emblock​

Width: NUM_TX_LANES
Dir: OUT
Clock Domain: tx_sys_clock

  • This output accompanies and qualifies the most significant byte of each lane of the current tx_lane_data bus as a start of extended multi-block delimiter.

Tx IP SYSREF and Alignment Ports​

tx_sysref​

Width: 1
Dir: IN
Clock Domain: tx_sys_clock

  • A positive edge detect on this signal is treated as a SYSREF event in the JESD Tx IP.

tx_lmfc_pulse​

Width: 1
Dir: OUT
Clock Domain: tx_sys_clock

  • Single cycle pulse, indicating an LMFC (multi-frame boundary) event in the JESD Tx IP.
    Note: This is applicable only in 8b/10b mode.

tx_lemc_pulse​

Width: 1
Dir: OUT
Clock Domain: tx_sys_clock

  • Single cycle pulse, indicating an LEMC (extended multi-block boundary) event in the JESD Tx IP.
    Note: This is applicable only in 64b/66b mode.

tx_sysref_realign_count​

Width: 4
Dir: OUT
Clock Domain: tx_sys_clock

  • Indicates the number of times a SYSREF event caused a re-alignment of the LMFC/LEMC timing in the JESD Tx IP (after the last reset event).
    This stops incrementing after a reaching a max value of 'hF.

tx_clr_sysref_realign_count​

Width: 1
Dir: IN
Clock Domain: tx_sys_clock

  • When 1, clears the tx_sysref_realign_count.

Reserved Test Ports​

testport1_in​

Width: 256
Dir: IN
Clock Domain: NA

  • Reserved. Must be tied to all 0's.

testport1_out​

Width: 256
Dir: OUT
Clock Domain: NA

  • Reserved. Leave unconnected.

testport2_in​

Width: 256
Dir: IN
Clock Domain: NA

  • Reserved. Must be tied to all 0's.

testport2_out​

Width: 256
Dir: OUT
Clock Domain: NA

  • Reserved. Leave unconnected.

testport3_in​

Width: 1050
Dir: IN
Clock Domain: NA

  • Reserved. Must be tied to all 0's.

testport3_out​

Width: 1050
Dir: OUT
Clock Domain: NA

  • Reserved. Leave unconnected.