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7 Timing Constraint Guidelines

The TI204c JESD IP has been architected to simplify the definition of timing constraints, and also minimize the overall P&R effort and runtime incurred by the Vivado tools. The following table lists the primary ports that need timing constraints and the associated guidelines.

note

In addition to the table below, it is recommended that the designer use the constraints file provided with the customized reference design as the primary starting point for specification of timing constraints.

mgt_refclk_p​

  • Constraint type: Clock
  • Guidelines: Define a clock on this port with the appropriate frequency.

mgt_freerun_clock​

  • Constraint type: Clock
  • Guidelines: Define a clock on this port with the appropriate frequency.

master_reset_n​

  • Constraint type: False Path
  • Guidelines: The master reset is asynchronous and should be set as false path.

rx_sync_clock​

  • Constraint type: Clock and False Paths
  • Guidelines:
    • Define a clock on this port with the appropriate frequency.
    • Define rx_sync_clock and mgt_freerun_clock as asynchronous to each other.

tx_sync_clock​

  • Constraint type: Clock
  • Guidelines:
    • Define a clock on this port with the appropriate frequency.
    • Define tx_sync_clock and mgt_freerun_clock as asynchronous to each other.

mgt_rx_usrclk2 domain​

  • Constraint type: Multi-cycle paths
  • Guidelines: Set a multi-cycle path of 50ns with the –datapathonly option for all paths between mgt_rx_usrclk2 and rx_sync_clock. This constraint is necessary only if the RX_BUFFER_TYPE attribute is set to "NORM".

mgt_tx_usrclk2 domain​

  • Constraint type: Multi-cycle paths
  • Guidelines: Set a multi-cycle path of 50ns with the –datapathonly option for all paths between mgt_tx_usrclk2 and tx_sync_clock. This constraint is necessary only if the TX_BUFFER_TYPE attribute is set to "NORM". If the attribute is set to "NONE", this constraint should be excluded.

cfg_*​

  • Constraint type: False Paths
  • Guidelines: All inputs to the IP with the name cfg_* can be set as false paths. This is because they need to be held static before the IP is released from reset.

rx_release_all_lanes​

  • Constraint type: Multi-cycle Path
  • Guidelines: This signal is generated by ANDing all of the rx_all_lanes_locked signals of various IP's (as described in section 6.7). While both signals lie in the rx_sys_clock clock domain, the rx_all_lanes_locked output is aligned to an LEMC/LMFC pulse boundary, and the rx_release_all_lanes input is not sampled until the next LEMC/LMFC pulse boundary. This creates a multi-cycle path that can be specified if Rx synchronization signals are being passed across FPGA / SLR boundaries and timing closure is a challenge at the targeted rx_sys_clock frequency.