Skip to main content

MPSoC Device Configuration

Zynq UltraScale+ XCZU7EV MPSoC devices use a multi-stage boot process as described in the "Boot and Configuration" chapter of the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085). Switch SW6 configuration option settings are listed in Table 2-4.

Table 2-4: Switch SW6 Configuration Option Settings

Boot ModeMode Pins [3:0]Mode SW6 [4:1]
JTAG0000ON, ON, ON, ON
QSPI320010(1)ON, ON, OFF, ON
SD1110OFF, OFF, OFF, ON

Notes:

  1. Default switch setting.
  2. For DIP SW6, in relation to the arrow, moving the switch toward the label ON is a 0. DIP switch labels 1 through 4 are equivalent to mode pins 0 through 3.

JTAG​

Vivado® Design Suite, SDK, or third-party tools can establish a JTAG connection to the Zynq UltraScale+ MPSoC device through one of these provided JTAG interfaces:

  • Xilinx platform USB or cable PC4 connector (J8)
  • Arm 20-pin JTAG connector (J6)
  • FTDI FT232HL USB-to-JTAG bridge U152 with micro-USB connector (J2)

Quad SPI​

To boot from the dual Quad SPI nonvolatile configuration memory:

  1. Store a valid Zynq UltraScale+ MPSoC boot image in the Quad SPI flash devices connected to the MIO Quad SPI interface.
  2. Set the boot mode pins SW6 [3:0] PS_MODE[3:0] as indicated in Table 2-4 for Quad SPI32.
  3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in Figure 2-1.

SD​

To boot from an SD card:

  1. Store a valid Zynq UltraScale+ MPSoC boot image file on to an SD card (plugged into SD socket J100) connected to the MIO SD interface.
  2. Set the boot mode pins SW6 [3:0] PS_MODE[3:0] as indicated in Table 2-4 for SD.
  3. Either power-cycle or press the power-on reset (POR) pushbutton. SW6 is callout 46 in Figure 2-1.

See the Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) [Ref 3] for more information about Zynq UltraScale+ MPSoC configuration options.