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Resets

The reset inputs and outputs on the JESD204C core are as shown in the following table.

tx/rx_core_reset​

  • This reset input is asynchronous and active-High.
  • This reset input will reset the JESD204C core logic but does not reset the AXI4-Lite register interface, so all programmed register values will be maintained.

s_axi_aresetn​

  • This reset input must be synchronized with the AXI4-Lite interface clock.
  • This reset input will reset the AXI4-Lite register interface.

tx/rx_aresetn​

  • This reset output is synchronous to tx/rx_core_clk.
  • This output is an AXI4-Stream interface reset signal to be used with the AXI4-Stream RX/TX Data and Cmd interfaces.

Versal Adaptive SoCs​

chN_txmstdatapathreset1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_txmstreset1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_txpmaresetdone1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_txuserrdy1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_rxmstdatapathreset1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_rxmstreset1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_rxpmaresetdone1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_rxuserrdy1​

  • This active-High reset output is connected to the Versal Adaptive SoC Transceiver using Block Automation. The output is driven by internal logic in the JESD204C core. N = Lanes - 1

chN_rxmstresetdone1​

  • This active-High reset input is connected to the Versal Adaptive SoC Transceiver using Block Automation. The input holds the JESD204C core in reset until it asserts High. N = Lanes - 1

reset_all2​

  • Reset output to the gtwiz_versal subsystem reset controller. Resets TX PLL and datapath.

reset_tx_pll_and_datapath2​

  • Reset output to the gtwiz_versal subsystem reset controller. Resets TX PLL and datapath.

reset_tx_datapath2​

  • Reset output to the gtwiz_versal subsystem reset controller. Resets TX datapath only.

reset_tx_done2​

  • Reset Done input from the gtwiz_versal subsystem reset controller. Active-High when TX reset sequence is complete.

reset_rx_datapath2​

  • Reset output to the gtwiz_versal subsystem reset controller. Resets RX datapath only.

reset_rx_done2​

  • Reset Done input from the gtwiz_versal subsystem reset controller. Active-High when RX reset sequence is complete.

UltraScale+/UltraScale Devices​

tx/rx_reset_gt​

  • This reset output must be connected to the JESD204_PHY core. This signal is used to initiate a JESD204_PHY GT reset sequence.

tx/rx_reset_done​

  • This input must be connected to the JESD204_PHY core. This signal is used to hold the JESD204C core in reset until completion of the JESD204_PHY GT reset sequence.
  • Note: A Low input on this port forces the JESD204C core into a reset state.
  1. These ports are present only when you select the Legacy GT Wizard in JESD204C GUI.
  2. These ports are present only when you select the GT Wizard subsystem in JESD204C GUI.