Skip to main content

SYSREF

SYSREF Timing​

When the JESD204C is used in Subclass 1, the SYSREF signal is the master timing reference for the system. To achieve accurate deterministic latency, the SYSREF signal must be captured synchronously to the core clock. To achieve this, the SYSREF period must be a multiple of 4-byte clock periods for 8B10B linecoding and 8-byte clock periods for 64B66B linecoding. This is because the core uses a 4-byte or 8-byte internal datapath for 8B10B and 64B66B, respectively.

SYSREF Type​

The accurate capture of SYSREF is critical in Subclass 1 operation. The JESD204C Specification allows SYSREF to be generated in any of the following ways:

  • Periodic
  • One-shot
  • Gapped Periodic

For maximum flexibility, the JESD204C core provides several options for how SYSREF is handled for Subclass 1 operation.

Because the JESD204C core operates using a 32-bit (4-byte) or 64-bit (8-byte) datapath, if a periodic or gapped periodic SYSREF is used in the system, the following conditions must be met:

  • For 64B66B linecoding, the period must be an integer multiple of the Extended Multiblock period.
  • For 8B10B linecoding, the period must be an integer multiple of the multiframe period. It must also be a multiple of 4-byte clocks. Care must be taken to ensure both of these conditions are met if the multiframe period is not a multiple of 4-byte clocks.

SYSREF Handling​

SYSREF Delay​

The SYSREF Delay bits in the CTRL_SYSREF register can be used to add delay to the SYSREF signal after it is captured (see Table 15). This allows the effective phase of the local multiframe clock (LMFC)/ local extended multiblock clock (LEMC) to be adjusted. The value programmed into the SYSREF delay register equates to the number of core clock cycles that SYSREF will be delayed by.

For 8B10B linecoding, the deterministic latency mechanism, as defined in the JESD204C standard, requires that the multiframe size be larger than the maximum possible delay across the link. In practice, this can be difficult to achieve, particularly with small frame sizes. However, as long as the multiframe size is greater than the maximum variation between lanes in delay across the link, then deterministic latency can be achieved. A potential issue occurs when the maximum lane delay variation causes the overall latency to straddle the boundary between two adjacent LMFC periods. In such a case, latency variations of exactly one LMFC period can be observed between system restarts. In this case, the SYSREF might be delayed to adjust the LMFC boundary position to alleviate the problem.

For 64B66B linecoding, the deterministic latency mechanism defined in the JESD204C standard requires that the maximum variation between lanes in delay across the link be less than the Extended Multiblock size. However, the alignment buffer in the 64B66B RX IP core is fixed at a size of two multiblocks. Care should be taken when designing systems where the number of Multiblocks in an Extended Multiblock (MB_IN_EMB) is greater than two because this can cause the buffers to overflow if more than two Multiblocks of data need to be stored before the next LEMC buffer release point. The SYSREF Delay register can be used to offset the phase of the LEMC clock from SYSREF such that even for large values of MB_IN_EMB the RX IP core LEMC can be adjusted such that the required amount of data to be buffered is less than two Multiblocks. The TX IP core also has this register to aid system latency optimization.

SYSREF Always​

The SYSREF Always bit in the CTRL_SYSREF register provides the JESD204C core with a programmable option allowing the choice of how a periodic SYSREF is used internally (see Table 15).

  • When SYSREF Always is set to 0, only an initial SYSREF event seen after reset (or on link resynchronization) is used to align the internal LMFC counter. All subsequent SYSREF events will be ignored.
  • When SYSREF Always is set to 1, all SYSREF events are used to (re)align the LMFC counter. This setting requires that the SYSREF period be a correct multiple of the Multiframe/Extended Multiblock periods.

SYSREF Required​

The SYSREF required bit in the CTRL_SYSREF register provides the JESD204C core with a programmable option allowing the choice of whether a SYSREF event is required or not for the link to restart after a resync request (see Table 15).

  • When SYSREF Required is set to 0, a resync request will automatically restart the link.
  • When SYSREF Required is set to 1, a resync request will stall until a new SYSREF event has been detected.

Capturing SYSREF​

The synchronous capture of SYSREF is critical to the deterministic latency mechanism of JESD204C. By default, no constraints are applied to the SYSREF input. However, the required timing of the SYSREF input can be checked using the report_datasheet command in the Vivado Design Suite.

An example timing diagram is shown in the following figure. This example uses the following settings:

  • core_clk period = 6.4 ns (6.25 Gb/s line rate with 8B10B linecoding)

In this example, the report_datasheet command gives a setup of 4.6 ns and hold of -1.5 ns for the SYSREF pin.

Figure: SYSREF Timing Example

Note: For the JESD204C IP core, SYSREF is sampled on the rising edge of the core clock.

The easiest method to ensure that a design reliably captures SYSREF is to use a programmable clock generator chip that allows fine delay adjustment of its outputs, to generate all the JESD204C clocks and SYSREF signals in the system. This allows the delay between core clock and SYSREF to be adjusted to meet the setup and hold requirements achieved by your design. It is also possible to use an MMCM to adjust the phase of core clock internally to align with the setup and hold requirements.

After a reset, a JESD204C core configured for subclass 1 operation requires at least one SYSREF event to align the internal LMFC counter, and bring up the link:

  • A receive core requires an initial SYSREF event to align the LMFC, and then asserts SYNC on the next LMFC boundary when code group sync has been achieved. The core does not assert SYNC until an initial SYSREF event is detected.
  • A transmit core requires a SYSREF event to align the LMFC. The core begins ILA transmission on an LMFC boundary after SYNC is asserted. The core does not begin ILA transmission until an initial SYSREF event is detected.

The system must ensure that SYSREF to the JESD204C core is generated after the core has completed reset. This is of particular importance if the system is operating a one-shot SYSREF.

After initial bring-up, if a link resynchronization is requested (by the deassertion of SYNC by the receiving device), the desired core behavior relative to SYSREF can be controlled using the SYSREF Required control bit in the CTRL_SYSREF Handling register.

  • When SYSREF Required is set to 0, no SYSREF event is required for the link to re-synchronize (the assumption is that LMFC counters continue to free-run and remain valid).
    • A receive core asserts SYNC on the next LMFC boundary after code group sync.
    • A transmit core transmits the ILA sequence on the next LMFC boundary after SYNC is asserted.
  • When SYSREF Required is set to 1, a SYSREF event is required for the link to reestablish SYNC following a resync request. In this case, the behavior is the same as the initial link bring up detailed earlier. This setting is particularly important in systems where a One-Shot SYSREF is used, or where SYSREF is periodic, but SYSREF Always is set to 0.

After a reset, a JESD204C core configured for subclass 1 operation requires at least one SYSREF event to align the internal LMBC counter, and bring up the link:

  • A receiver core requires an initial SYSREF event to align the LMBC. The core does not start the LEMC counter until an initial SYSREF event is detected.
  • A transmitter core requires a SYSREF event to align the LMBC. The core does not begin transmission of multiblocks until an initial SYSREF event is detected.

Therefore, a link cannot achieve multiblock lock until after a SYSREF event has been seen by both a transmitter and a receiver.

The system must ensure that SYSREF to the JESD204C core is generated after the core has completed reset. This is of particular importance if the system is operating a One-shot SYSREF.

After initial bring-up, if a link resynchronization is requested by the receiving device, the desired core behavior relative to SYSREF can be controlled using the SYSREF Required control bit in the CTRL_SYSREF Handling register.

  • When SYSREF Required is set to 0, no SYSREF event is required for the link to resynchronize (the assumption is that LMBC counters continue to free-run and remain valid).
    • A receive core will re-acquire multiblock lock and output received data on the next LMBC boundary.
    • A transmit core will continue to transmit multiblock data.
  • When SYSREF Required is set to 1, a SYSREF event is required for the link to reestablish SYNC following a resync request. In this case, the behavior is the same as the initial link bring-up detailed earlier. This setting is particularly important in systems where a one-shot SYSREF is used, or where SYSREF is periodic but SYSREF Always is set to 0.