Register Space

The JESD204C core is configured using an AXI4-Lite Register Interface. The register map is shown in the following table.

note

The JESD204C AXI4-Lite interface currently does not support outstanding transactions. The ongoing transaction data access must end completely before the next transaction starts. Otherwise, the new transaction data might get incorrectly stored at the address of the previous transaction data.

The RX and TX cores share a common address map and register definitions where possible, exceptions are highlighted.

tip

Recommended: AMD recommends that if significant configuration changes are made using the control registers (in particular, changes to framing parameters), the core should be reset to ensure that the link is resynchronized using the updated parameters.

Register Address Space

AXI4-Lite	Registers Name	64B66B		8B10B
		TX Access Type	RX Access Type	TX Access Type	RX Access Type
0x000	IP_VERSION	R	R	R	R
0x004	IP_CONFIG	R	R	R	R
0x020	RESET	R/W	R/W	R/W	R/W
0x024	CTRL_ENABLE	R/W	R/W	N/A	N/A
0x028	CTRL_TX_SYNC	N/A	N/A	R/W	N/A
0x030	CTRL_MB_IN_EMB	R/W	R/W	N/A	N/A
0x034	CTRL_SUB_CLASS	R/W	R/W	R/W	R/W
0x038	CTRL_META_MODE	R/W	R/W	N/A	N/A
0x03C	CTRL_8B10B_CFG	N/A	N/A	R/W	R/W
0x040	CTRL_LANE_ENA	R/W	R/W	R/W	R/W
0x044	CTRL_RX_BUF_ADV	N/A	R/W	N/A	R/W
0x048	CTRL_TEST_MODE	R/W	R/W	R/W	R/W
0x04C	CTRL_RX_MBLOCK_TH	N/A	R/W	N/A	N/A
0x050	CTRL_SYSREF	R/W	R/W	R/W	R/W
0x054	STAT_LOCK_DEBUG	N/A	R	N/A	N/A
0x058	STAT_RX_ERR	N/A	N/A	N/A	R
0x05C	STAT_RX_DEBUG	N/A	N/A	N/A	R
0x060	STAT_STATUS	R	R	R	R
0x064	CTRL_IRQ	R/W	R/W	R/W	R/W
0x068	STAT_IRQ	R	R	R	R
0x070	CTRL_TX_ILA_CFG0	N/A	N/A	R/W	N/A
0x074	CTRL_TX_ILA_CFG1	N/A	N/A	R/W	N/A
0x078	CTRL_TX_ILA_CFG2	N/A	N/A	R/W	N/A
0x07C	CTRL_TX_ILA_CFG3	N/A	N/A	R/W	N/A
0x080	CTRL_TX_ILA_CFG4	N/A	N/A	R/W	N/A
0x4001	(Lane 0) STAT_RX_BUF_LVL	N/A	R	N/A	R
0x4041	(Lane 0) CTRL_TX_ILA_LID	N/A	N/A	R/W	N/A
0x4101	(Lane 0) STAT_RX_ERROR_CNT0	N/A	R	N/A	N/A
0x4141	(Lane 0) STAT_RX_ERROR_CNT1	N/A	R	N/A	N/A
0x4601	(Lane 0) CTRL_TX_GT	R/W	R/W	R/W	R/W
0x4641	(Lane 0) CTRL_RX_GT	R/W	R/W	R/W	R/W
0x4681	(Lane 0) CTRL_TX_VERSAL_GTY/GTYP	R/W	R/W	R/W	R/W
0x46C1	(Lane 0) CTRL_TX_VERSAL_GTM	R/W	R/W	R/W	R/W

¹ As shown, lane 0 registers start at 0x400. Lane 1 registers occupy the equivalent space starting at 0x480, lanes 2-7 follow the same pattern (that is, lane 2 = 0x500, lane 3 = 0x580, etc.).

IP_VERSION

Bits	Default Value	Description
31:24	-	Version: Major
23:16	-	Version: Minor
15:8	-	Version: Revision
7:0	-	Reserved (read 0x00)

IP_CONFIG

Bits	Default Value	Description
18	-	1 = FEC Included 0 = FEC not included (FEC is only available when configured for 64B66B)
17	-	1 = Core is 64B66B 0 = Core is 8B10B
16	-	1 = Core is TX 0 = Core is RX
3:0	-	Number of lanes in core.

RESET

Bits	Default Value	Description
31:24 1	-	gt_mst_reset_busy[7:0] 1-bit per enabled GT lane. These bits show the inversion of the mstresetdone inputs from the Versal adaptive SoC GTs.
23:16 1	-	gt_pma_reset_busy[7:0] 1-bit per enabled GT lane. These bits show the inversion of the pmaresetdone inputs from the Versal adaptive SoC GTs.
7 1	-	gt_reset_busy 1 = GTs are still in reset 0 = GTs have finished reset
6 1	-	gt_powergood input state This bit shows the inversion of the gt_powergood input from the Versal adaptive SoC GT. 1 = gt_powergood not completed 0 = gt_powergood completed
5	-	Core Reset Register State 1 = tx/rx_reset asserted 0 = tx/rx_reset deasserted
4	-	Core External Reset Pin State 1 = tx/rx_core_reset asserted 0 = tx/rx_core_reset deasserted
1 1	0	Reset type 1 = Initiates a Datapath only reset 0 = Initiates a PLL+ Datapath reset Reset type should be asserted first followed by the reset bit 0.
0	0	Reset (not self-clearing) 1 = put core into reset 0 = Release core from reset After setting this bit to 1 and clearing back to 0, this bit will read back 1 until the reset process has completed.

¹ For Versal adaptive SoCs only.

CTRL_ENABLE

Bits	Default Value	Description
1	0	Enable Data Interface. 1 = Enables the AXI4-Stream Data interface and transmits/receives data on the link. 0 = The link will be transmitting/receiving scrambled 0s
0	0	Enable Cmd interface. 1 = Enables the AXI4-Stream Cmd interface and the associated processing of the sync header meta data. 0 = Cmd words will be zeroed.

CTRL_TX_SYNC

Bits	Default Value	Description
0	0	tx_sync_force. Force on 8B10B transmitter. When set to 1, this register overrides the value on the tx_sync pin.

CTRL_MB_IN_EMB

Bits	Default Value	Description
7:0	0x1	Number of multiblocks in an extended multiblock. Program this register with the actual value. Note: 0 is not valid.

CTRL_SUB_CLASS

Bits	Default Value	Description
1:0	0x1	Sub Class: 0 = Subclass 0 1 = Subclass 1 2 = Subclass 2 (8B10B only)

CTRL_META_MODE

Bits	Default Value	Description
1:0	0x0	Meta Mode: 0 = CRC12 1 = N/A 2 = CMD 3 = FEC

CTRL_8B10B_CFG

Bits	Default Value	Description
31:24	0x3	ILA multiframes. Multiframes in the Transmitted Initial Lane Alignment Sequence. Parameter Range: 4–256; program the register with required value minus 1.
21:20	0x0	Reserved. Must be set to zero.
19	0	1 = Enable Link Error counters (Link errors are counted and reported using Link Error Count registers per lane) 0 = Disable Link Error counters
18	0	Error Reporting via sync: 1 = Error reporting using SYNC interface Enabled 0 = Error reporting using SYNC interface Disabled
17	1	ILA Required: 1 = Enable ILA Support 0 = Disable ILA Support
16	1	Scrambling: 1 = Enable Scrambling 0 = Disable Scrambling
12:8	0xF	Frames per Multiframe (K) Parameter range 1–32; Program register with required value minus 1 (for example, for K = 16, 0xF should be programmed)
7:0	0x1	Octets per Frame (F) Parameter range 1–256; Program register with required value minus 1 (for example, for F = 4, 0x03 should be programmed)

CTRL_LANE_ENA

Bits	Default Value	Description
7:0	0xFF	Lane Enable. Each bit enables the corresponding lane. The core will not process data for lanes that are disabled.

CTRL_TEST_MODE

Bits	Default Value	Description
11:8 1	0x0	PRBS mode select (Versal adaptive SoCs only): 4'b0000: Standard operation mode. (PRBS off) 4'b0001: PRBS-7 4'b0010: PRBS-9 4'b0011: PRBS-15 4'b0100: PRBS-23 4'b0101: PRBS-31 4'b0110: PRBS-13
2:0 2	0x0	Test mode select (8B10B mode): 000 = Normal operation 001 = Transmit receive /K28.5/ indefinitely 2 010 = Synchronize as normal then transmit/receive repeated ILA sequences. 2 101 = Transmit Modified Random Pattern RPAT (TX only) 1 111 = Transmit Scrambled Jitter Pattern JSPAT (TX only) 1

¹ These test modes are only applicable to the JESD204C 8B10B transmitter IP. They are used to set the transceiver to output specific patterns that might be used to evaluate the electrical characteristics of a link using tools such as IBERT. A JESD204C 8B10B receiver core will not synchronize or function if these test patterns are received.

CTRL_RX_MBLOCK_TH

Bits	Default Value	Description
2:0	0x0	MB lock threshold. How many correct/incorrect multiblock alignment markers are required to achieve/lose multiblock lock. The actual value used is 1 plus the number in this register.

CTRL_SYSREF

Bits	Default Value	Description
23:16	0x0	(For 64b66b cores only) SYSRF Delay: Add additional delay to SYSRF alignment LEMC. 0xFF = 255 core_clk cycles delay ... 0x00 = 0 core_clk cycles delay. This register is used to retard the phase of the LEMC.
19:16	0x0	SYSRF Delay: Add additional delay to SYSRF alignment of LMFC. 1111 = 15 core_clk cycles delay ... 0000 = 0 core_clk cycles delay This register is used to retard the phase of the LMFC.
10:8	0x0	SYSRF Tolerance: Specify a tolerance value in core_clk cycles for SYSRF detection when in SYSRF Always mode. If a SYSRF event is detected within +/- tolerance core_clk cycles from its expected position, no error signal will be issued.
1	0	SYSRF Required on Re-Sync 1 = Following a Link Re-Sync event, a SYSRF event is required to re-align the local LMFC/LEMC before the link will operate. 0 = No SYSREF is required to restart a link after a Re-sync event.
0	0	SYSREF Always 1 = The core will align the LMFC/LEMC counter on all SYSREF events. 0 = The core will only align the LMFC/LEMC counter on the first SYSREF event following a reset, all subsequent SYSREF events will be ignored.

STAT_LOCK_DEBUG

Bits	Default Value	Description
23:16	-	Lane indicator multiblock aligned. 1 bit per lane. Set to 1 when multiblock alignment is achieved. 0 otherwise.
7:0	-	Lane indicator 64B66B sync header aligned. 1 bit per lane. Set to 1 when sync header alignment is achieved. 0 otherwise.

STAT_RX_ERR

Bits	Default Value	Description
31:28	-	RX Error status lane 7
27:24	-	RX Error status lane 6
23:20	-	RX Error status lane 5
19:16	-	RX Error status lane 4
15:12	-	RX Error status lane 3
11:8	-	RX Error status lane 2
7:4	-	RX Error status lane 1
3:0	-	RX Error status lane 0 Bit 3: unused Bit 2: Unexpected K-character(s) received Bit 1: Disparity Error(s) received Bit 0: Not in table Error(s) received Each bit indicates that 1 or more errors of that type have been received in Lane 0 because the register was last read. All status bits are cleared to 0 on read of this register.

STAT_RX_DEBUG

Bits	Default Value	Description
31:28	-	Link Debug status Lane 7 as per lane 0
27:24	-	Link Debug status Lane 6 as per lane 0
23:20	-	Link Debug status Lane 5 as per lane 0
19:16	-	Link Debug status Lane 4 as per lane 0
15:12	-	Link Debug status Lane 3 as per lane 0
11:8	-	Link Debug status Lane 2 as per lane 0
7:4	-	Link Debug status Lane 1 as per lane 0
3:0	-	Link Debug status Lane 0 Bit 3: 1 = Start of Data was Detected 1 Bit 2: 1 = Start of ILA was Detected 1 Bit 1: 1 = Lane has Code Group Sync 2 Bit 0: 1 = Lane is currently receiving K28.5's (BC alignment characters) 2

¹ The status bits 3:2 latch when set and are cleared on read or when the core is reset. If the core is streaming data when these bits are cleared, they are instantly set again. The purpose of these bits is to detect whether these conditions have occurred because SYNC was asserted.

² The status bits 1:0 show instantaneous status.

STAT_STATUS

Bits	Default Value	Description
15	-	8B10B Alignment Error: 1 = An 8B10B RX misalignment has been detected. Misalignment is determined by monitoring the Multiframe framing characters. If eight consecutive framing characters are detected in misaligned positions, then this bit is asserted.
14	-	8B10B RX started: 1 = The link has started outputting data on the AXI4-Stream port. This bit is applicable to an 8B10B RX only.
13	-	8B10B CGS status: 1 = The link has achieved Code Group Sync. This bit is applicable to an 8B10B RX only.
12	-	8B10B SYNC status: 1 = The receiver has signaled SYNC has been achieved. This bit is applicable to an 8B10B link only.
10	-	Buffer Overflow error. 1 = The receiver buffer has overflowed.
5	-	64B66B Multiblock Lock Status: 1 = Multiblock lock achieved on all lanes. This bit is a logical AND of the individual lane status bits.
4	-	64B66B Sync Header Lock Status: 1 = Sync Header lock achieved on all lanes. This bit is a logical AND of the individual lane status bits.
2	-	SYSREF error. A sysref was detected out of phase with the local extended multiblock clock.
1	-	SYSREF captured.
0	-	Interrupt pending.

CTRL_IRQ

Bits	Default Value	Description
14	0	1 = Enable interrupt on 8B10B RX AXI4-Stream data start.
13	0	1 = Enable interrupt on 8B10B RX Resync request.
12	0	1 = Enable interrupt on 8B10B SYNC assertion.
10	0	1 = Enable Interrupt on overflow Error.
9	0	1 = Enable Interrupt on 64B66B FEC Error.
8	0	1 = Enable Interrupt on 64B66B CRC Error.
7	0	1 = Enable Interrupt on 64B66B Multiblock Error.
6	0	1 = Enable Interrupt on 64B66B Block Sync Error.
5	0	1 = Enable Interrupt on Loss of 64B66B Multiblock Lock.
4	0	1 = Enable Interrupt on Loss of 64B66B Sync Header Lock.
2	0	1 = Enable Interrupt on SYSREF Error.
1	0	1 = Enable Interrupt on SYSREF Received.
0	0	Global Interrupt Enable: Must be set for any interrupt to function.

STAT_IRQ

Bits	Default Value	Description
14	-	1 = 8B10B RX AXI4-Stream data start interrupt triggered.
13	-	1 = 8B10B RX Resync request interrupt triggered.
12	-	1 = 8B10B SYNC assertion interrupt triggered.
10	-	1 = Overflow Error Interrupt triggered.
9	-	1 = 64B66B FEC Error detected Interrupt triggered.
8	-	1 = 64B66B CRC Error detected Interrupt triggered.
7	-	1 = 64B66B Multiblock Error detected Interrupt triggered.
6	-	1 = 64B66B Block Sync Error detected Interrupt triggered.
5	-	1 = 64B66B Multiblock Lock Status Interrupt triggered.
4	-	1 = 64B66B Sync Header Lock Status Interrupt triggered.
2	-	1 = SYSREF Error Interrupt triggered.
1	-	1 = SYSREF Received Interrupt triggered.

CTRL_TX_ILA_CFG0

Bits	Default Value	Description
11:8	0x0	BID (Bank ID). Binary value.
7:0	0x0	DID (Device ID). Binary value.

CTRL_TX_ILA_CFG1

Bits	Default Value	Description
31:26	-	Reserved
25:24	0x0	CS (Control bits per Sample). Binary value.
23:21	-	Reserved
20:16	0x0	N' (Total bits per Sample). Binary value minus 1.
15:13	-	Reserved
12:8	0x0	N (Converter Resolution). Binary value minus 1.
7:0	0x0	M (Converters per Device). Binary value minus 1.

CTRL_TX_ILA_CFG2

Bits	Default Value	Description
28:24	0x0	CF (Control Words per Frame). Binary value.
16	0	HD (High Density format)
12:8	0x0	S (Samples per Converter per Frame). Binary value minus 1.

CTRL_TX_ILA_CFG3

Bits	Default Value	Description
31:17	-	Reserved
16	0	ADJDIR (Adjust Direction) [Subclass 2 Only]. Binary value.
15:9	-	Reserved
8	0	PHADJ (Phase Adjust Request) [Subclass 2 Only]. Binary value.
7:4	-	Reserved
3:0	0x0	ADJCNT (Phase Adjust Count) [Subclass 2 Only]. Binary value. RX: captured configuration data from the ILA sequence (per lane). TX: Sets the values to be transmitted in the ILA sequence for all lanes.

CTRL_TX_ILA_CFG4

Bits	Default Value	Description
15:8	0x0	RES2 (Reserved Field 2)
7:0	0x0	RES1 (Reserved Field 1)

STAT_RX_BUF_LVL ¹

Bits	Default Value	Description
9:0	-	Buffer fill level. The amount of data in the receiver buffer for lane 0. For 64B66B linecoding: The value returned is the number of 64-bit words in the buffer. For 8B10B Linecoding: The value returned is the number of bytes in the buffer.

¹ This is a Per Lane Register.

CTRL_TX_ILA_LID ¹

Bits	Default Value	Description
31:21	-	Reserved
20:16	L	Number of lanes per link (binary value minus 1). The default value for all lanes is L (total number of lanes minus 1). These values should be programmed when: • Not all lanes in the generated IP core are enabled. • A single TX core is used to drive multiple DAC devices. • Multiple TX cores are combined to create links with more than eight lanes.
15:5	-	Reserved
4:0	N	ID of lane N. Value can be anywhere between 0 and 31. The default value N is set to the lane number. For interfaces using more than 8 lanes and hence multiple JESD204C cores, this register should be programmed to ensure each lane has the correct identifier.

¹ This is a Per Lane Register.

STAT_RX_ERROR_CNT0 ¹

Bits	Default Value	Description
31:16	-	CRC error counter.
15:8	-	64B66B Multiblock alignment error counter.
7:0	-	64B66B Sync Header alignment error counter.

¹ This is a Per Lane Register. The counts are cumulative and are cleared on read or reset. The counts should be cleared with a register read when a link has been successfully established.

STAT_RX_ERROR_CNT1 ¹

Bits	Default Value	Description
31:16	-	64B66B FEC uncorrected errors counter.
15:0	-	64B66B FEC corrected errors counter.

¹ This is a Per Lane Register.

STAT_LINK_ERR_CNT ¹

Bits	Default Value	Description
31:0	-	Link Error Count Count of total received link errors (per lane) when Link Error Counters is Enabled. Errors counted are Disparity or Not In Table errors indicated by the lane. The error counter can be reset by disabling and re-enabling the Link Error Counters Enable, bit 19 in the CTRL_8B10B_CFG register.

¹ This is a Per Lane Register.

STAT_TEST_ERR_CNT ¹

Bits	Default Value	Description
31:0	-	Test Mode Error Count Count of Errors received in Data link Layer test modes. Test Mode = 001 (Continuous K28.5): counts any non K28.5 characters received Test Mode = 010 (Continuous ILA): counts any unexpected characters received This count resets to zero on transition to an active test mode and retains any count value on transition out of an active test mode.

¹ This is a Per Lane Register.

STAT_TEST_ILA_CNT ¹

Bits	Default Value	Description
31:0	-	Test Mode ILA Count Count of total ILA Sequences received when Test Mode = 010 (Continuous ILA) This count resets to zero on transition to Test Mode = 010, and retains any count value on transition out of test mode.

¹ This is a Per Lane Register.

STAT_TEST_MF_CNT ¹

Bits	Default Value	Description
31:0	-	Test Mode Multiframe Count Count of total ILA Multiframes received when Test Mode = 010 (Continuous ILA) This count resets to zero on transition to Test Mode = 010 and retains any count value on transition out of test mode.

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG0 ¹

Bits	Default Value	Description
31:11	-	Reserved
10:8	-	JESDV (JESD204 version): 000 = JESD204A 001 = JESD204B 010 = JESD204C
7:3	-	Reserved
2:0	-	SUBCLASS: 000 = Subclass0 001 = Subclass1 010 = Subclass2

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG1 ¹

Bits	Default Value	Description
31:8	-	Reserved
7:0	-	F (Octets per Frame). Binary value minus 1.

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG2 ¹

Bits	Default Value	Description
31:5	-	Reserved
4:0	-	K (Frames per Multiframe). Binary value minus 1.

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG3 ¹

Bits	Default Value	Description
31:29	-	Reserved
28:24	-	L (Lanes per Link). Binary value minus 1.
23:21	-	Reserved
20:16	0x0	LID (Lane ID). Binary value.
15:12	-	Reserved
11:8	0x0	BID (Bank ID). Binary value.
7:0	0x0	DID (Device ID). Binary value.

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG4 ¹

Bits	Default Value	Description
31:26	-	Reserved
25:24	-	CS (Control bits per Sample). Binary value.
23:21	-	Reserved
20:16	-	N' (Total bits per Sample). Binary value minus 1.
15:13	-	Reserved
12:8	-	N (Converter Resolution). Binary value minus 1.
7:0	-	M (Converters per Device). Binary value minus 1.

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG5 ¹

Bits	Default Value	Description
31:29	-	Reserved
28:24	0x0	CF (Control Words per Frame). Binary value.
23:17	-	Reserved
16	0	HD (High Density format)
15:13	-	Reserved
12:8	0x0	S (Samples per Converter per Frame). Binary value minus 1.
0	-	SCR (Scrambling Enable) [RX only, not writeable for TX] 1 = enabled

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG6 ¹

Bits	Default Value	Description
31:17	-	Reserved
16	0	ADJDIR (Adjust Direction) [Subclass 2 Only]. Binary value.
15:9	-	Reserved
8	0	PHADJ (Phase Adjust Request) [Subclass 2 Only]. Binary value.
7:4	-	Reserved
3:0	0x0	ADJCNT (Phase Adjust Count) [Subclass 2 Only]. Binary value. RX: captured configuration data from the ILA sequence (per lane). TX: Sets the values to be transmitted in the ILA sequence for all lanes.

¹ This is a Per Lane Register.

CTRL_RX_ILA_CFG7 ¹

Bits	Default Value	Description
31:24	-	Reserved
23:16	0x0	FCHK (Checksum) [RX only, not writeable for TX]. Binary value.
15:8	0x0	RES2 (Reserved Field 2)
7:0	0x0	RES1 (Reserved Field 1)

¹ This is a Per Lane Register.

CTRL_TX_GT ¹

Bits	Default Value	Description
31:5	-	Reserved
4	0	TXINHIBIT Set High to inhibit transmission of TX data
3	0	TXELECIDLE Set High to force idle signal on transmitter output
2:1	0x0	TXPD TX power down
0	0	TXPOLARITY Set High to invert the polarity of the outgoing TX data

¹ This is a Per Lane Register for Versal adaptive SoCs only.

CTRL_RX_GT ¹

Bits	Default Value	Description
31:3	-	Reserved
2:1	0x0	RXPD RX power down
0	0	RXPOLARITY Set High to invert the polarity of the incoming RX data.

¹ This is a Per Lane Register for Versal adaptive SoCs only.

CTRL_TX_VERSAL_GTY/GTYP ¹

Bits	Default Value	Description
31:15	–	Reserved
14:10	0x0	TXPOSTCURSOR Transmitter post-cursor pre-emphasis control
9:5	0x0	TXPRECURSOR Transmitter pre-cursor pre-emphasis control
4:0	0x18	TXDIFCFTRL Driver swing control

¹ This is a Per Lane Register for Versal adaptive SoCs only.

CTRL_TX_VERSAL_GTM ¹

Bits	Default Value	Description
31	–	Reserved
30:25	0x0	TXPOSTCURSOR Transmitter post-cursor pre-emphasis control
24:19	0x0	TXPRECURSOR3 Transmitter pre-cursor3 pre-emphasis control
18:13	0x0	TXPRECURSOR2 Transmitter pre-cursor2 pre-emphasis control
12:7	0x0	TXPRECURSOR Transmitter pre-cursor pre-emphasis control
6:0	0x0	TXMAINCURSOR Driver swing control

¹ This is a Per Lane Register for GTM Versal adaptive SoCs only.