6.4 Device Functional Modes
The device can be configured to operate in a number of functional modes. These modes are described in this section.
6.4.1 Low Power Mode and High Performance Mode
Device power consumption can be reduced at the tradeoff of performance by programming the device into the Low Power Mode. This mode is only available when operating at 1 GSPS or less and is recommended to only be used for 1st Nyquist zone applications. The default operating mode is High Performance Mode which is enabled by the default register values. Table 6-12 shows the register writes to switch between the lowest power configuration of Low Power Mode and High Performance Mode. These writes should only be performed when CAL_EN is set to 0 and JESD_EN is set to 0.
The magnitude of the glitch during the transition between ADC cores during background calibration and low power background calibration is affected by the setting of the LOW_POWER3 register setting (Address (=) (0\times 29B) ). A lower power can be traded off vs larger glitch magnitude. The ADC output during the transition between ADC cores for low power mode is shown in Figure 6- 10 and the power dissipation change vs LOW_POWER3 setting is shown in Figure 6- 11. A setting of 4 reduces the glitch to the same magnitude as high performance mode.
| Figure 6-10 Background Calibration Core Transition In Low Power Mode | Figure 6-11 Power Dissipation Change vs LOW_POWER3 register setting |
|---|---|
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In low power background calibration mode, the timing of the ADC transition can be controlled by setting register LP_TRIG = 1. The ADC transition will occur in the ADC output data between 500 and 1000 ADC sample clocks after triggering by the CALTRIG ball or SPI write to CAL_SOFT_TRIG register (Address = 0x6C).
Foreground calibration mode has no ADC core transitions and no glitch.
6.4.2 JESD204C Modes
The device can be programmed for a number JESD204C output formats. Table 6-13 summarizes the basic operating mode configuration parameters and whether they are user configured or derived.
| PARAMETER | DESCRIPTION | USER CONFIGURED OR DERIVED | VALUE |
|---|---|---|---|
| JMODE | JESD204C operating mode, automatically derives the rest of the JESD204C parameters | User configured | Set by JMODE |
| R | Number of bits transmitted per lane per ADC core sampling clock cycle. The JESD204C line rate is the sampling clock frequency (fs) times R. This parameter sets the SerDes PLL multiplication factor. | Derived | See Table 6-15 |
| K | Number of frames per multiframe (8B/10B mode) | User configured | Set by KM1, see the allowed values in Table 6-15. This parameter is ignored in 64B/66B modes. |
| E | Number of multibocks per extended multiblock (64B/66B mode) | Derived | Always set to ‘1’ in ADC12QJ1600-EP. This parameter is ignored in 8B/10B modes. |
There are a number of parameters required to define the JESD204C transport layer format, all of which are sent across the link during the initial lane alignment sequence in 8B/10B mode. 64B/66B mode does not use the ILAS, however the transport layer uses the same parameters. In the device, most parameters are automatically derived based on the selected JMODE; however, a few are configured by the user. Table 6-14 describes these parameters.
| PARAMETER | DESCRIPTION | USER CONFIGURED OR DERIVED | VALUE |
|---|---|---|---|
| ADJCNT | LMFC adjustment amount (not applicable) | Derived | Always 0 |
| ADJDIR | LMFC adjustment direction (not applicable) | Derived | Always 0 |
| BID | Bank ID | Derived | Always 0 |
| CF | Number of control words per frame | Derived | Always 0 |
| CS | Control bits per sample | Derived | Always set to 0 in ILAS, see Table 6-15 for actual usage |
| DID | Device identifier, used to identify the link | User configured | Set by DID, see Table 6-16 |
| F | Number of octets (bytes) per frame (per lane) | Derived | See Table 6-15 |
| HD | High-density format (samples split between lanes) | Derived | Always 0 |
| JESDV | JESD204 standard revision | Derived | Always 1 |
| K | Number of frames per multiframe | User configured | Set by the KM1 register |
| L | Number of serial output lanes per link | Derived | See Table 6-15 |
| LID | Lane identifier for each lane | Derived | See Table 6-16 |
| M | Number of converters used to determine lane bit packing; may not match number of ADC channels in the device | Derived | See Table 6-15 |
| N | Sample resolution (before adding control and tail bits) | Derived | See Table 6-15 |
| N' | Bits per sample after adding control and tail bits | Derived | See Table 6-15 |
| S | Number of samples per converter (M) per frame | Derived | See Table 6-15 |
| SCR | Scrambler enabled | User configured | Set by SCR |
| SUBCLASSV | Device subclass version | Derived | Always 1 |
| RES1 | Reserved field 1 | Derived | Always 0 |
| RES2 | Reserved field 2 | Derived | Always 0 |
| CHKSUM | Checksum for ILAS checking (sum of all above parameters modulo 256) | Derived | Computed based on parameters in this table |
Configuring the device is made easy by using a single configuration parameter called JMODE. Using Table 6-15 the correct JMODE value can be found for the desired operating mode. The modes listed are the only available operating modes. This tables also gives a range and allowable step size for the K parameter (set by KM1), which sets the multiframe length in number of frames.
| OPERATING MODE | USER-SPECIFIED PARAMETER | DERIVED PARAMETERS | INPUT CLOCK RANGE (MHz) | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| JMODE | K [Min:Step:Max] | Encoding | N | CS | N’ | CF | L | M | F | S | HD | E | R (Fbit / Fclk) | ||
| 12-Bit, 64B/66B, 6 Lanes | 6 | 128(2) | 64B/66B | 12 | 0 | 12 | 0 | 6 | 4 | 2 | 2 | 1 | 1 | 8.25 | 500-1600 |
| 12-Bit, 8B/10B, 8 Lanes | 0 | 4:4:256 | 8B/10B | 12 | 0 | 12 | 0 | 8 | 8(1) | 8 | 5 | 0 | — | 8 | 500-1600 |
| 12-Bit, 8B/10B, 6 Lanes | 1 | 16:16:256 | 8B/10B | 12 | 0 | 12 | 0 | 6 | 4 | 2 | 2 | 1 | — | 10 | 500-1600 |
| 8-Bit, 8B/10B, 4 Lanes | 2 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 4 | 4 | 1 | 1 | 0 | — | 10 | 500-1600 |
| 10-Bit, 8B/10B, 4 Lanes | 3 | 32:32:256 | 8B/10B | 10 | 0 | 10 | 0 | 4 | 4 | 5 | 4 | 0 | — | 12.5 | 500-1372.8 |
| 12-Bit, 64B/66B, 3 Lanes | 4 | 128(2) | 64B/66B | 12 | 0 | 12 | 0 | 3 | 4 | 2 | 1 | 1 | 1 | 16.5 | 500-1040 |
| 8-Bit, 64B/66B, 2 Lanes | 5 | 128(2) | 64B/66B | 8 | 0 | 8 | 0 | 2 | 4 | 2 | 1 | 0 | 1 | 16.5 | 500-1040 |
| 12-Bit, 64B/66B, 6 Lanes | 6 | 128(2) | 64B/66B | 12 | 0 | 12 | 0 | 6 | 4 | 2 | 2 | 1 | 1 | 8.25 | 500-1600 |
| 8-Bit, 64B/66B, 4 Lanes | 7 | 256(2) | 64B/66B | 8 | 0 | 8 | 0 | 4 | 4 | 1 | 1 | 0 | 1 | 8.25 | 500-1600 |
| 12-Bit, 64B/66B, 4 Lanes | 8 | 256(2) | 64B/66B | 12 | 0 | 12 | 0 | 4 | 4 | 3 | 2 | 0 | 3 | 12.375 | 500-1386.7 |
| 8-Bit, 8B/10B, 8 Lanes | 9 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 8 | 4 | 1 | 2 | 0 | — | 5 | 500-1600 |
| 10-Bit, 8B/10B, 8 Lanes | 10 | 32:32:256 | 8B/10B | 10 | 0 | 10 | 0 | 8 | 8(1) | 5 | 4 | 0 | — | 6.25 | 500-1600 |
| 2 Ch, 12-Bit, 8B/10B, 8 Lanes | 11 | 4:4:256 | 8B/10B | 12 | 0 | 12 | 0 | 8 | 8(1) | 8 | 5 | 0 | — | 4 | 500-1600 |
| 2 Ch, 8-Bit, 8B/10B, 8 Lanes | 12 | 32:32:256 | 8B/10B | 8 | 0 | 8 | 0 | 8 | 2 | 1 | 4 | 0 | — | 2.5 | 500-1600 |
| 2 Ch, 10-Bit, 8B/10B, 8 Lanes | 13 | 32:32:256 | 8B/10B | 10 | 0 | 10 | 0 | 8 | 8(1) | 5 | 4 | 0 | — | 3.125 | 500-1600 |
| 12-Bit, 64B/66B, 8 Lanes | 14 | 256(2) | 64B/66B | 12 | 0 | 12 | 0 | 8 | 8(1) | 3 | 2 | 0 | 3 | 6.1875 | 500-1600 |
| 2-ch, 12-Bit, 64B/66B, 8 Lanes | 15 | 256(2) | 64B/66B | 12 | 0 | 12 | 0 | 8 | 8(1) | 3 | 2 | 2 | 3 | 3.09375 | 500-1600 |
- (1) M equals L in these modes to allow the samples to be sent in time-order over L lanes without unnecessary buffering. The M parameter does not represent the actual number of converters. Interleave the M sample streams from each link in the receiver to produce the correct sample data; see mode diagrams for more details.
- (2) In the 64B/66B modes, the K parameter is not directly programmable. K is related to E and F according to the equation K = 8 x 32 x E/F. K is not an actual parameter of the 64B/66B link layer.
The device has a total of 8 high-speed output drivers. The lanes and their derived configuration parameters are described in Table 6-16. For a specified JMODE, the lowest indexed lanes are used and the higher indexed lanes are automatically powered down. Always route the lowest indexed lanes to the logic device.
| DEVICE PIN DESIGNATION | DID (User Configured) | LID (Derived) |
|---|---|---|
| D0± | Set by DID | 0 |
| D1± | Set by DID | 1 |
| D2± | Set by DID | 2 |
| D3± | Set by DID | 3 |
| D4± | Set by DID | 4 |
| D5± | Set by DID | 5 |
| D6± | Set by DID | 6 |
| D7± | Set by DID | 7 |
6.4.2.1 JESD204C Transport Layer Data Formats
The ADC core output samples are formatted in a specific fashion for each JMODE setting based on the transport layer settings for that JMODE. The following tables show the specific mapping formats for a single frame for each JMODE. The symbol definitions used in the JMODE tables is provided in Table 6- 17. In all mappings the tail bits (T) are 0 (zero). All samples are formatted as MSB first, LSB last.
| NOTATION | DESCRIPTION |
|---|---|
| An | Sample n from channel A |
| Bn | Sample n from channel B |
| Cn | Sample n from channel C |
| Dn | Sample n from channel D |
| T | Tail bits, always set to 0 |
6.4.2.3 Redundant Data Mode (Alternate Lanes)
JMODEs that use four or less lanes allow the use of redundancy on the JESD204C output. For instance, a system may have two FPGAs or ASICs connected to a single device, if the FPGA or ASIC is deemed the weak point in system reliability. In this example system, only one FPGA or ASIC operates at a time with the redundant FPGA or ASIC only being enabled if a fault is detected in the default FPGA or ASIC. To use this mode, the lower four SerDes lanes (D3-D0) must be routed to a single FPGA or ASIC and the upper four SerDes lanes (D7-D4) routed to the redundant FPGA or ASIC. The lower four lanes are the "default" lanes and the upper four lanes are the "alternate" lanes. The desired lanes are chosen by setting ALT_LANES parameter to 0 for the default lanes or 1 for the alternate lanes. Only one set of SerDes outputs can be operated at a time.
6.4.3 Power-Down Modes
The PD input pin allows the device devices to be entirely powered down. Power-down can also be controlled by MODE. The serial data output drivers are disabled when PD is high. When the device returns to normal operation, the JESD204 link must be re-established and the ADC pipelines contain meaningless information so the system must wait a sufficient time for the data to be flushed. The register configuration and calibration data is maintained during power down. A calibration cycle (foreground or background calibration) may be needed to return to optimal performance if the temperature changes drastically during the duration of power down. Pairs of channels can also be powered down using the CH_EN register. Do not use CH_EN to power down all four channels, use MODE or the PD pin instead.
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