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5.1 Parameter / Attribute list

The following table lists all the parameters (attributes) of the JESD IP.

IP_ID​

Default: 0

  • Integer value used to assign an ID to the IP.
    This ID is passed to the Verilog wrapper that contains the MGT transceiver instance. This can be used to select transceivers of different attributes, in case an FPGA design has multiple JESD IP's, with each IP containing a different transceiver

IP_TYPE​

Default: "RXTX"

  • Controls the type of IP generated:
    • "RXTX": IP contains logic for both Rx and Tx JESD datapaths
    • "RX": IP contains logic for Rx JESD datapaths
      • Tx related attributes can be left at default
      • Tx related input ports can be tied to 0's
      • Tx related output ports are driven to defaults and can be left unconnected
    • "TX": IP contains logic for Tx JESD path
      • Rx related attributes can be left at default
      • Rx related input ports can be tied to 0's
      • Rx related output ports are driven to defaults and can be left unconnected

IP_PROTOCOL​

Default: 810

  • Controls the protocol supported by the IP
    • 810: IP contains logic for 8b/10b mode of the JESD protocol
      • 64b/66b related attributes can be left at default
      • 64b/66b related input ports can be tied to 0's
      • 64b/66b related output ports are driven to defaults
    • 6466: IP contains logic for 64b/66b mode of the JESD protocol
      • 8b/10b related attributes can be left at default
      • 8b/10b related input ports can be tied to 0's
      • 8b/10b related output ports are driven to defaults

ADC_RES​

Default: 12

  • Resolution of the ADC connected to the Rx IP

DAC_RES​

Default: 12

  • Resolution of the DAC connected to the Tx IP

GT_TYPE​

Default: "GTYP"

  • Type of transceiver in the FPGA
    • GTYP : GTY transceiver, UltraScale+ device
    • GTY : GTY transceiver, UltraScale device
    • GTHP : GTH transceiver, UltraScale+ device
    • GTH : GTH transceiver, UltraScale device
    • GTX : GTX transceiver, 7000 series device
    • GTP : GTP transceiver, 7000 series device

NUM_REFCLK_BUFFERS​

Default: 2

  • Number of Reference Clock Buffer pins used for the MGT
    • This refers to the number of LVDS reference clock pairs only
    • The internal routing of reference clocks within/across the Quads of the transceiver may vary based on the application

NUM_QUADS​

Default: 2

  • Number of Quads used in the transceiver

NUM_RX_LANES​

Default: 8

  • Number of Rx channels / lanes used in the transceiver

RX_LN_IDX_WIDTH​

Default: 3

  • Log (base2) of NUM_RX_LANES (rounded up to nearest power of 2)
    • Eg: If NUM_RX_LANES = 4, RX_LN_IDX_WIDTH = 2
    • Eg: If NUM_RX_LANES = 12, RX_LN_IDX_WIDTH = 4

RX_LN_DATA_WIDTH​

Default: 64

  • Data width of each lane of the Rx IP. Allowed values (and supported transceivers) are
    • 32 : GTYP, GTY, GTHP, GTH, GTX, GTP
    • 64 : GTYP, GTY, GTHP, GTH, GTX
    • 128 : GTYP (64b/66b mode only)

NUM_TX_LANES​

Default: 8

  • Number of Tx channels / lanes used in the transceiver

TX_LN_IDX_WIDTH​

Default: 3

  • Log (base2) of NUM_TX_LANES (rounded up to nearest power of 2)
    • E.g.: If NUM_TX_LANES = 4, TX_LN_IDX_WIDTH = 2
    • E.g.: If NUM_TX_LANES = 12, TX_LN_IDX_WIDTH = 4

TX_LN_DATA_WIDTH​

Default: 64

  • Data width of each lane of the Tx IP. Allowed values (and supported transceivers) are
    • 32 : GTYP, GTY, GTHP, GTH, GTX, GTP
    • 64 : GTYP, GTY, GTHP, GTH, GTX
    • 128 : GTYP (64b/66b mode only)

GT_USERIO_IN_WIDTH​

Default: 16

  • Data width of the MGT transceiver related general purpose IN port

GT_USERIO_OUT_WIDTH​

Default: 16

  • Data width of the MGT transceiver related general purpose OUT port

PARAM_RX_F​

Default: 1

  • 'F' parameter of the 8b/10b protocol for the Rx IP. This indicates the number of octets per frame

PARAM_RX_K​

Default: 32

  • 'K' parameter of the 8b/10b protocol for the Rx IP. This indicates the number of frames per multi-frame

PARAM_RX_HD​

Default: 0

  • 'HD' parameter of the 8b/10b protocol for the Rx IP. When set to 1, it indicates that the bits representing a sample are not contained entirely within one lane

PARAM_TX_N​

Default: 16

  • 'N' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_NPR​

Default: 16

  • 'Nprime' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_CS​

Default: 0

  • 'CS' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_F​

Default: 1

  • 'F' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_K​

Default: 32

  • 'K' parameter of the 8b/10b protocol for the Tx IP Note: The value of (PARAM_TX_F * PARAM_RX_K * 8) must be an integral multiple of TX_LN_DATA_WIDTH. The K (or K minus 1) value in the DAC should be programmed in accordance with this requirement

PARAM_TX_DEVID​

Default: 0

  • 'DEVID' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_BANKID​

Default: 0

  • 'BANKID' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_HD​

Default: 0

  • 'HD' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_M​

Default: 8

  • 'M' parameter of the 8b/10b protocol for the Tx IP

PARAM_TX_S​

Default: 4

  • 'S' parameter of the 8b/10b protocol for the Tx IP

PARAM_RX_E​

Default: 4

  • 'E' parameter of the 64b/66b protocol for the Rx IP

PARAM_TX_E​

Default: 1

  • 'E' parameter of the 64b/66b protocol for the Tx IP

RX_SYSREF_OFFSET​

Default: 0

  • Number of sequential stages between the SYSREF at the input pin of the FPGA and the rx_sysref input pin of the JESD IP. This is applicable for designs requiring deterministic latency

TX_SYSREF_OFFSET​

Default: 0

  • Number of sequential stages between the SYSREF at the input pin of the FPGA and the tx_sysref input pin of the JESD IP. This is applicable for designs requiring deterministic latency

RX_RBD_COUNT_WIDTH​

Default: 10

  • Width of the delay counter used for controlling the buffer release timing of the Rx IP. This is applicable for designs requiring deterministic latency

RX_LMFC_TARGET_COUNT​

Default: 0

  • This value controls the number of rx_sys_clock cycles required for one period of the system multi-frame. This is reserved for 8b/10b encoding. This is applicable for designs requiring deterministic latency.
    It is recommended that this value be set to 0, as the IP will compute the timing parameters internally. A non 0 value should be used only if either of the following conditions is true:
    • RX_LN_DATAWIDTH = 32, and rx_sys_clock is not LineRate/40
    • RX_LN_DATAWIDTH = 64, and rx_sys_clock is not LineRate/80

RX_LEMC_TARGET_COUNT​

Default: 0

  • This value controls the number of rx_sys_clock cycles required for one period of the system extended multi-block. This is reserved for 64b/66b encoding. This is applicable for designs requiring deterministic latency
    It is recommended that this value be set to 0, as the IP will compute the timing parameters internally. A non 0 value should be used only if either of the following conditions is true:
    • RX_LN_DATAWIDTH = 32, and rx_sys_clock is not LineRate/33
    • RX_LN_DATAWIDTH = 64, and rx_sys_clock is not LineRate/66
    • RX_LN_DATAWIDTH = 128, and rx_sys_clock is not LineRate/132

RX_BUFFER_TYPE​

Default: "NORM"

  • This parameter should be left unmodified from the value in the reference design

RX_BUFFER_RATIO​

Default: 1

  • This parameter should be left unmodified from the value in the reference design

TX_BUFFER_TYPE​

Default: "NORM"

  • This parameter should be left unmodified from the value in the reference design

RX_TL_ENABLED​

Default: "NO"

  • This parameter should be left unmodified from the value in the reference design

TL_PARAM1​

Default: 1

  • This parameter should be left unmodified from the value in the reference design

TL_PARAM2​

Default: 0

  • This parameter should be left unmodified from the value in the reference design

TL_PARAM3​

Default: 1

  • This parameter should be left unmodified from the value in the reference design

SAMPLES_PER_CYCLE_PER_LANE​

Default: 4

  • This parameter should be left unmodified from the value in the reference design

TL_TYPE​

Default: "NORM"

  • This parameter should be left unmodified from the value in the reference design